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| rev. 2.5 april 2003 1/153 st72334j/n, st72314j/n, st72124j 8-bit mcu with single voltage flash memory, adc, 16-bit timers, spi, sci interfaces n memories C 8k or 16k program memory (rom or single voltage flash) with read-out protection and in-situ programming (remote isp) C 256 bytes eeprom data memory (with r ead- out protection option in rom devices) C 384 or 512 bytes ram n clock, reset and supply management C enhanced reset system C enhanced low voltage supply supervisor with 3 programmable levels C clock sources: crystal/ceramic resonator os- cillators or rc oscillators, external clock, backup clock security system C 4 power saving modes: halt, active-halt, wait and slow C beep and clock-out capabilities n interrupt management C 10 interrupt vectors plus trap and reset C 15 external interrupt lines (4 vectors) n 44 or 32 i/o ports C 44 or 32 multifunctional bidirectional i/o lines: C 21 or 19 alternate function lines C 12 or 8 high sink outputs n 4 timers C configurable watchdog timer C realtime base C two 16-bit timers with: 2 input captures (only one on timer a), 2 output compares (only one on timer a), external clock input on timer a, pwm and pulse generator modes n 2 communications interfaces C spi synchronous serial interface C sci asynchronous serial interface (lin com- patible) n 1 analog peripheral C 8-bit adc with 8 input channels (6 only on st72334jx, not available on st72124j2) n instruction set C 8-bit data manipulation C 63 basic instructions C 17 main addressing modes C 8 x 8 unsigned multiply instruction C true bit manipulation n development tools C full hardware/software development package device summary tqfp44 10 x 10 psdip42 psdip56 tqfp64 14 x 14 features st72124j2 st72314j2 st72314j4 st72314n2 st72314n4 st72334j2 st72334j4 st72334n2 st72334n4 program memory - bytes 8k 8k 16k 8k 16k 8k 16k 8k 16k ram (stack) - bytes 384 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256) eeprom - bytes - - - -- 256 256 256 256 peripherals watchdog, two 16-bit timers, spi, sci -adc operating supply 3.2v to 5.5 v cpu frequency up to 8 mhz (with up to 16 mhz oscillator) operating temperature -40c to +85c (-40c to +105/125c optional) packages tqfp44 / sdip42 tqfp64 / sdip56 tqfp44 / sdip42 tqfp64 / sdip56 1
table of contents 153 2/153 2 1 preamble: st72c334 versus st72e331 specification . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 5 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 5.3 structural organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 in-situ programming (isp) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 memory read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 data eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 6.3 memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 data eeprom register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 read-out protection option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 8.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 8.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.1 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.3 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.4 clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.5 supply, reset and clock register description . . . . . . . . . . . . . . . . . . . . . 32 10 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.1 non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.3 peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.4 active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table of contents 3/153 3 12.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.1 i/o port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.2 i/o port alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.3 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 14 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.2 main clock controller with real time clock timer (mcc/rtc) . . . . . . . 52 14.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.5 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.6 8-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 15 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 16 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 16.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 16.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 16.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 16.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 16.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 16.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 16.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 16.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 16.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 16.10 timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 16.11 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 135 16.12 8-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 17 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 17.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 17.2 soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 18 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . 144 18.1 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 44 18.2 transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 18.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 18.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 19 important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 19.1 sci baud rate registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 20 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 st72334j/n, st72314j/n, st72124j 4/153 to obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet. please also pay special attention to the section important notes on page 151 st72334j/n, st72314j/n, st72124j 5/153 1 preamble: st72c334 versus st72e331 specification new features available on the st72c334 n 8 or 16k flash/rom with in-situ programming and read-out protection n new adc with a better accuracy and conversion time n new configurable clock, reset and supply system n new power saving mode with real time base: active halt n beep capability on pf1 n new interrupt source: clock security system (css) or main clock controller (mcc) st72c334 i/o configuration and pinout n same pinout as st72e331 n pa6 and pa7 are true open drain i/o ports without pull-up (same as st72e331) n pa3, pb3, pb4 and pf2 have no pull-up configuration (all i/os present on tqfp44) n pa5:4, pc3:2, pe7:4 and pf7:6 have high sink capabilities (20ma on n-buffer, 2ma on p-buffer and pull-up). on the st72e331, all these pads (except pa5:4) were 2ma push-pull pads without high sink capabilities. pa4 and pa5 were 20ma true open drains. new memory locations in st72c334 n 20h: miscr register becomes miscr1 register (naming change) n 29h: new control/status register for the mcc module n 2bh: new control/status register for the clock, reset and supply control. this register replaces the wdgsr register keeping the wdogf flag compatibility. n 40h: new miscr2 register st72334j/n, st72314j/n, st72124j 6/153 2 introduction the st72334j/n, st72314j/n and st72124j de- vices are members of the st7 microcontroller fam- ily. they can be grouped as follows: C st72334j/n devices are designed for mid-range applications with data eeprom, adc, spi and sci interface capabilities. C st72314j/n devices target the same range of applications but without data eeprom. C st72124j devices are for applications that do not need data eeprom and the adc peripher- al. all devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set. the st72c334j/n, st72c314j/n and st72c124j versions feature single-voltage flash memory with byte-by-byte in-situ pro- gramming (isp) capability. under software control, all devices can be placed in wait, slow, active-halt or halt mode, reducing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. for easy reference, all parametric data are located in section 16 on page 107 . figure 1. general block diagram 8-bit core alu address and data bus osc1 ispsel control program (8k or 16k bytes) v ss reset port f pf7,6,4,2:0 (6-bit) timer a beep port a ram (384 or 512 bytes) port c 8-bit adc v dda v ssa port b pb7:0 port e pe7:0 sci timer b pa7:0 port d pd7:0 spi pc7:0 (8-bit) v dd eeprom (256 bytes) watchdog multi osc lvd osc2 memory mcc/rtc + clock filter (8-bit for n versions) (5-bit for j versions) (8-bit for n versions) (5-bit for j versions) (6-bit for n versions) (2-bit for j versions) (8-bit for n versions) (6-bit for j versions) st72334j/n, st72314j/n, st72124j 7/153 3 pin description figure 2. 64-pin tqfp package pinout (n versions) v dda v ssa v dd_3 v ss_3 mco / pf0 beep / pf1 pf2 nc ocmp1_a / pf4 nc icap1_a / (hs) pf6 extclk_a / (hs) pf7 ain4 / pd4 ain5 / pd5 ain6 / pd6 ain7 / pd7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ei2 ei3 ei0 ei1 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 ain0 / pd0 ain1 / pd1 ain2 / pd2 ain3 / pd3 (hs) pe4 (hs) pe5 (hs) pe6 (hs) pe7 pa1 pa0 pc7 / ss pc6 / sck / ispclk pc5 / mosi pc4 / miso / ispdata pc3 (hs) / icap1_b pc2 (hs) / icap2_b pc1 / ocmp1_b pc0 / ocmp2_b v ss_0 v dd_0 v ss_1 v dd_1 pa3 pa2 v dd _2 osc1 osc2 v ss _2 nc nc reset ispsel pa7 (hs) pa6 (hs) pa5 (hs) pa4 (hs) nc nc pe1 / rdi pe0 / tdo (hs) 20ma high sink capability ei x associated external interrupt vector st72334j/n, st72314j/n, st72124j 8/153 pin description (contd) figure 3. 56-pin sdip package pinout (n versions) 52 51 50 49 48 47 46 45 44 43 42 41 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 53 54 55 56 pb4 pb5 beep / pf1 mco / pf0 v ssa v dda ain7 / pd7 ain6 / pd6 ain5 / pd5 ain2 / pd2 ain1 / pd1 ain0 / pd0 pb7 pb6 ain4 / pd4 ain3 / pd3 pb3 pb2 ispsel reset v ss _2 osc2 osc1 v dd _2 pe0 / tdo pe5 (hs) pe6 (hs) pe7 (hs) pb0 pb1 pe4 (hs) pe1 / rdi ei3 ei0 ei2 ei1 21 20 17 18 19 v dd_0 extclk_a / (hs) pf7 icap1_a / (hs) pf6 ocmp1_a / pf4 pf2 40 39 38 37 36 v ss_1 pa4 (hs) pa5 (hs) pa6 (hs)i pa7 (hs) 23 22 ocmp2_b / pc0 v ss_0 28 27 24 25 26 mosi / pc5 ispdata/ miso / pc4 icap1_b / (hs) pc3 icap2_b / (hs) pc2 ocmp1_b / pc1 35 34 pa3 v dd_1 33 32 31 30 29 pc6 / sck / ispclk pc7 / ss pa0 pa1 pa2 (hs) 20ma high sink capability ei x associated external interrupt vector st72334j/n, st72314j/n, st72124j 9/153 pin description (contd) figure 4. 44-pin tqfp and 42-pin sdip package pinouts (j versions) mco / pf0 beep / pf1 pf2 ocmp1_a / pf4 icap1_a / (hs) pf6 extclk_a / (hs) pf7 v dd_0 v ss_0 ain5 / pd5 v dda v ssa 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 ei2 ei3 ei0 ei1 pb3 pb4 ain0 / pd0 ain1 / pd1 ain2 / pd2 ain3 / pd3 ain4 / pd4 pe1 / rdi pb0 pb1 pb2 pc6 / sck / ispclk pc5 / mosi pc4 / miso / ispdata pc3 (hs) / icap1_b pc2 (hs) / icap2_b pc1 / ocmp1_b pc0 / ocmp2_b v ss_1 v dd_1 pa3 pc7 / ss v ss _2 reset ispsel pa7 (hs) pa6 (hs) pa5 (hs) pa4 (hs) pe0 / tdo v dd _2 osc1 osc2 38 37 36 35 34 33 32 31 30 29 28 27 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 39 40 41 42 pb4 ain0 / pd0 ocmp2_b / pc0 extclk_a / (hs) pf7 icap1_a / (hs) pf6 ocmp1_a / pf4 pf2 beep / pf1 mco / pf0 ain5 / pd5 ain4 / pd4 ain3 / pd3 ain2 / pd2 ain1 / pd1 v ssa v dda pb3 pb2 pa4 (hs) pa5 (hs) pa6 (hs) pa7 (hs) ispsel reset v ss _2 v dd _2 pe0 / tdo pe1 / rdi pb0 pb1 osc1 osc2 ei3 ei0 ei2 ei1 21 20 17 18 19 mosi / pc5 ispdata / miso / pc4 icap1_b / (hs) pc3 icap2_b/ (hs) pc2 ocmp1_b / pc1 26 25 24 23 22 pc6 / sck / ispclk pc7 / ss pa3 v dd_1 v ss_1 (hs) 20ma high sink capability ei x associated external interrupt vector st72334j/n, st72314j/n, st72124j 10/153 pin description (contd) for external pin connection guidelines, refer to section 16 "electrical characteristics" on page 107 . legend / abbreviations for table 1 : type: i = input, o = output, s = supply input level: a = dedicated analog input in/output level: c = cmos 0.3v dd /0.7v dd , c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration: C input: float = floating, wpu = weak pull-up, int = interrupt 1) , ana = analog C output: od = open drain 2) , pp = push-pull refer to section 12 "i/o ports" on page 39 for more details on the software configuration of the i/o ports. the reset configuration of each pin is shown in bold. this configuration is valid as long as the device is in reset state. table 1. device pin description pin n pin name type level port main function (after reset) alternate function tqfp64 sdip56 qfp44 sdip42 input output input output float wpu int ana od pp 1 49 pe4 (hs) i/o c t hs x x x x port e4 2 50 pe5 (hs) i/o c t hs x x x x port e5 3 51 pe6 (hs) i/o c t hs x x x x port e6 4 52 pe7 (hs) i/o c t hs x x x x port e7 5 53 2 39 pb0 i/o c t x ei2 x x port b0 6 54 3 40 pb1 i/o c t x ei2 x x port b1 7 55 4 41 pb2 i/o c t x ei2 x x port b2 8 56 5 42 pb3 i/o c t x ei2 x x port b3 9 1 6 1 pb4 i/o c t x ei3 x x port b4 10 2 pb5 i/o c t x ei3 x x port b5 11 3 pb6 i/o c t x ei3 x x port b6 12 4 pb7 i/o c t x ei3 x x port b7 13 5 7 2 pd0/ain0 i/o c t x x x x x port d0 adc analog input 0 14 6 8 3 pd1/ain1 i/o c t x x x x x port d1 adc analog input 1 15 7 9 4 pd2/ain2 i/o c t x x x x x port d2 adc analog input 2 16 8 10 5 pd3/ain3 i/o c t x x x x x port d3 adc analog input 3 17 9 11 6 pd4/ain4 i/o c t x x x x x port d4 adc analog input 4 18 10 12 7 pd5/ain5 i/o c t x x x x x port d5 adc analog input 5 19 11 pd6/ain6 i/o c t x x x x x port d6 adc analog input 6 20 12 pd7/ain7 i/o c t x x x x x port d7 adc analog input 7 21 13 13 8 v dda s analog power supply voltage 22 14 14 9 v ssa s analog ground voltage 23 v dd_3 s digital main supply voltage st72334j/n, st72314j/n, st72124j 11/153 24 v ss_3 s digital ground voltage 25 15 15 10 pf0/mco i/o c t x ei1 x x port f0 main clock output (f osc /2) 26 16 16 11 pf1/beep i/o c t x ei1 x x port f1 beep signal output 27 17 17 12 pf2 i/o c t x ei1 x x port f2 28 nc not connected 29 18 18 13 pf4/ocmp1_a i/o c t x x x x port f4 timer a output compare 1 30 nc not connected 31 19 19 14 pf6 (hs)/icap1_a i/o c t hs x x x x port f6 timer a input capture 1 32 20 20 15 pf7 (hs)/extclk_a i/o c t hs x x x x port f7 timer a external clock source 33 21 21 v dd_0 s digital main supply voltage 34 22 22 v ss_0 s digital ground voltage 35 23 23 16 pc0/ocmp2_b i/o c t x x x x port c0 timer b output compare 2 36 24 24 17 pc1/ocmp1_b i/o c t x x x x port c1 timer b output compare 1 37 25 25 18 pc2 (hs)/icap2_b i/o c t hs x x x x port c2 timer b input capture 2 38 26 26 19 pc3 (hs)/icap1_b i/o c t hs x x x x port c3 timer b input capture 1 39 27 27 20 pc4/miso i/o c t x x x x port c4 spi master in / slave out data 40 28 28 21 pc5/mosi i/o c t x x x x port c5 spi master out / slave in data 41 29 29 22 pc6/sck i/o c t x x x x port c6 spi serial clock 42 30 30 23 pc7/ss i/o c t x x x x port c7 spi slave select (active low) 43 31 pa0 i/o c t x ei0 x x port a0 44 32 pa1 i/o c t x ei0 x x port a1 45 33 pa2 i/o c t x ei0 x x port a2 46 34 31 24 pa3 i/o c t x ei0 x x port a3 47 35 32 25 v dd_1 s digital main supply voltage 48 36 33 26 v ss_1 s digital ground voltage 49 37 34 27 pa4 (hs) i/o c t hs x x x x port a4 50 38 35 28 pa5 (hs) i/o c t hs x x x x port a5 51 39 36 29 pa6 (hs) i/o c t hs x t port a6 52 40 37 30 pa7 (hs) i/o c t hs x t port a7 53 41 38 31 ispsel i must be tied low in user mode. in pro- gramming mode when available, this pin acts as in-situ programming mode se- lection. 54 42 39 32 reset i/o c x x top priority non maskable interrupt (ac- tive low) 55 nc not connected 56 nc 57 43 40 33 v ss_3 s digital ground voltage 58 44 41 34 osc2 3) o resonator oscillator inverter output or capacitor input for rc oscillator pin n pin name type level port main function (after reset) alternate function tqfp64 sdip56 qfp44 sdip42 input output input output float wpu int ana od pp st72334j/n, st72314j/n, st72124j 12/153 notes : 1. in the interrupt input column, ei x defines the associated external interrupt vector. if the weak pull-up column (wpu) is merged with the interrupt column (int), then the i/o configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. in the open drain output column, t defines a true open drain i/o (p-buffer and protection diode to v dd are not implemented). see section 12 "i/o ports" on page 39 and section 16.8 "i/o port pin char- acteristics" on page 128 for more details. 3. osc1 and osc2 pins connect a crystal or ceramic resonator, an external rc, or an external source to the on-chip oscillator see section 3 "pin description" on page 7 and section 16.5 "clock and tim- ing characteristics" on page 116 for more details. 59 45 42 35 osc1 3) i external clock input or resonator oscilla- tor inverter input or resistor input for rc oscillator 60 46 43 36 v dd_3 s digital main supply voltage 61 47 44 37 pe0/tdo i/o c t x x x x port e0 sci transmit data out 62 48 1 38 pe1/rdi i/o c t x x x x port e1 sci receive data in 63 nc not connected 64 nc pin n pin name type level port main function (after reset) alternate function tqfp64 sdip56 qfp44 sdip42 input output input output float wpu int ana od pp st72334j/n, st72314j/n, st72124j 13/153 4 register & memory map as shown in the figure 5 , the mcu is capable of addressing 64k bytes of memories and i/o regis- ters. the available memory locations consist of 128 bytes of register locations, 384 or 512 bytes of ram, up to 256 bytes of data eeprom and 4 or 8 kbytes of user program memory. the ram space includes up to 256 bytes for the stack from 0100h to 01ffh. the highest address bytes contain the user reset and interrupt vectors. important: memory locations marked as re- served must never be accessed. accessing a re- served area can have unpredictable effects on the device. figure 5. memory map 0000h interrupt & reset vectors hw registers 027fh 0080h 16-bit addressing ram 007fh 0200h / 0280h 0bffh reserved 0080h (see table 2 ) 0c00h ffdfh ffe0h ffffh (see table 5 on page 34 ) 027fh c000h reserved 256 bytes data eeprom 0cffh 0d00h bfffh 00ffh 0100h 01ffh 0200h 8k bytes e000h 16k bytes program short addressing ram zero page 0080h 00ffh 01ffh 01ffh 384 bytes ram 512 bytes ram stack or 16-bit addressing ram 0100h memory program memory 8 kbytes e000h c000h 16 kbytes ffffh (128 bytes) (256 bytes) short addressing ram zero page stack or 16-bit addressing ram (128 bytes) (256 bytes) st72334j/n, st72314j/n, st72124j 14/153 register & memory map (contd) table 2. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a padr paddr paor port a data register port a data direction register port a option register 00h 1) 00h 00h r/w r/w r/w 2) 0003h reserved area (1 byte) 0004h 0005h 0006h port c pcdr pcddr pcor port c data register port c data direction register port c option register 00h 1) 00h 00h r/w r/w r/w 0007h reserved area (1 byte) 0008h 0009h 000ah port b pbdr pbddr pbor port b data register port b data direction register port b option register 00h 1) 00h 00h r/w r/w r/w 2) 000bh reserved area (1 byte) 000ch 000dh 000eh port e pedr peddr peor port e data register port e data direction register port e option register 00h 1) 00h 00h r/w r/w r/w 2) 000fh reserved area (1 byte) 0010h 0011h 0012h port d pddr pdddr pdor port d data register port d data direction register port d option register 00h 1) 00h 00h r/w r/w r/w 2) 0013h reserved area (1 byte) 0014h 0015h 0016h port f pfdr pfddr pfor port f data register port f data direction register port f option register 00h 1) 00h 00h r/w r/w r/w 0017h to 001fh reserved area (9 bytes) 0020h miscr1 miscellaneous register 1 00h r/w 0021h 0022h 0023h spi spidr spicr spisr spi data i/o register spi control register spi status register xxh 0xh 00h r/w r/w read only 0024h to 0028h reserved area (5 bytes) 0029h mcc mccsr main clock control / status register 01h r/w st72334j/n, st72314j/n, st72124j 15/153 002ah watchdog wdgcr watchdog control register 7fh r/w 002bh crsr clock, reset, supply control / status register 000x 000x r/w 002ch data-eeprom eecsr data-eeprom control/status register 00h r/w 002dh 0030h reserved area (4 bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tacr2 tacr1 tasr taic1hr taic1lr taoc1hr taoc1lr tachr taclr taachr taaclr taic2hr taic2lr taoc2hr taoc2lr timer a control register 2 timer a control register 1 timer a status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate counter high register timer a alternate counter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only 3) read only 3) r/w 3) r/w 3) 0040h miscr2 miscellaneous register 2 00h r/w 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate counter high register timer b alternate counter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci scisr scidr scibrr scicr1 scicr2 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 sci extended receive prescaler register reserved area sci extended transmit prescaler register c0h xxh 00xx xxxx xxh 00h 00h --- 00h read only r/w r/w r/w r/w r/w r/w address block register label register name reset status remarks st72334j/n, st72314j/n, st72124j 16/153 legend : x=undefined, r/w=read/write notes : 1. the contents of the i/o port dr registers are readable only in output configuration. in input configura- tion, the values of the i/o pins are returned instead of the dr register contents. 2. the bits corresponding to unavailable pins are forced to 1 by hardware, affecting accordingly the reset status value. these bits must always keep their reset value. 3. external pin not available. 0058h 006fh reserved area (24 bytes) 0070h 0071h adc adcdr adccsr data register control/status register xxh 00h read only r/w 0072h to 007fh reserved area (14 bytes) address block register label register name reset status remarks st72334j/n, st72314j/n, st72124j 17/153 5 flash program memory 5.1 introduction flash devices have a single voltage non-volatile flash memory that may be programmed in-situ (or plugged in a programming tool) on a byte-by- byte basis. 5.2 main features n remote in-situ programming (isp) mode n up to 16 bytes programmed in the same cycle n mtp memory (multiple time programmable) n read-out memory protection against piracy 5.3 structural organisation the flash program memory is organised in a single 8-bit wide memory block which can be used for storing both code and data constants. the flash program memory is mapped in the up- per part of the st7 addressing space and includes the reset and interrupt user vector area . 5.4 in-situ programming (isp) mode the flash program memory can be programmed using remote isp mode. this isp mode allows the contents of the st7 program memory to be up- dated using a standard st7 programming tools af- ter the device is mounted on the application board. this feature can be implemented with a minimum number of added components and board area im- pact. an example remote isp hardware interface to the standard st7 programming tool is described be- low. for more details on isp programming, refer to the st7 programming specification. remote isp overview the remote isp mode is initiated by a specific se- quence on the dedicated ispsel pin. the remote isp is performed in three steps: C selection of the ram execution mode C download of remote isp code in ram C execution of remote isp code in ram to pro- gram the user program into the flash remote isp hardware configuration in remote isp mode, the st7 has to be supplied with power (v dd and v ss ) and a clock signal (os- cillator and application crystal circuit for example). this mode needs five signals (plus the v dd signal if necessary) to be connected to the programming tool. this signals are: C reset : device reset Cv ss : device ground power supply C ispclk: isp output serial clock pin C ispdata: isp input serial data pin C ispsel: remote isp mode selection. this pin must be connected to v ss on the application board through a pull-down resistor. if any of these pins are used for other purposes on the application, a serial resistor has to be imple- mented to avoid a conflict if the other device forces the signal level. figure 6 shows a typical hardware interface to a standard st7 programming tool. for more details on the pin locations, refer to the device pinout de- scription. figure 6. typical remote isp interface 5.5 memory read-out protection the read-out protection is enabled through an op- tion bit. for flash devices, when this option is selected, the program and data stored in the flash memo- ry are protected against read-out piracy (including a re-write protection). when this protection option is removed the entire flash program memory is first automatically erased. however, the e 2 prom data memory (when available) can be protected only with rom devices. ispsel v ss reset ispclk ispdata osc1 osc2 v dd st7 he10 connector type to programming tool 10k w c l0 c l1 application 47k w 1 xtal st72334j/n, st72314j/n, st72124j 18/153 6 data eeprom 6.1 introduction the electrically erasable programmable read only memory can be used as a non volatile back- up for storing data. using the eeprom requires a basic access protocol described in this chapter. 6.2 main features n up to 16 bytes programmed in the same cycle n eeprom mono-voltage (charge pump) n chained erase and programming cycles n internal control of the global programming cycle duration n end of programming cycle interrupt flag n wait mode management figure 7. eeprom block diagram eecsr eeprom interrupt falling edge high voltage pump ie lat 0 0 0 0 0 pgm eeprom reserved detector eeprom memory matrix (1 row = 16 x 8 bits) address decoder data multiplexer 16 x 8 bits data latches row decoder data bus 4 4 4 128 128 address bus st72334j/n, st72314j/n, st72124j 19/153 data eeprom (contd) 6.3 memory access the data eeprom memory read/write access modes are controlled by the lat bit of the eep- rom control/status register (eecsr). the flow- chart in figure 8 describes these different memory access modes. read operation (lat=0) the eeprom can be read as a normal rom loca- tion when the lat bit of the eecsr register is cleared. in a read cycle, the byte to be accessed is put on the data bus in less than 1 cpu clock cycle. this means that reading data from eeprom takes the same time as reading data from eprom, but this memory cannot be used to exe- cute machine code. write operation (lat=1) to access the write mode, the lat bit has to be set by software (the pgm bit remains cleared). when a write access to the eeprom area occurs, the value is latched inside the 16 data latches ac- cording to its address. when pgm bit is set by the software, all the previ- ous bytes written in the data latches (up to 16) are programmed in the eeprom cells. the effective high address (row) is determined by the last eep- rom write sequence. to avoid wrong program- ming, the user must take care that all the bytes written between two programming sequences have the same high address: only the four least significant bits of the address can change. at the end of the programming cycle, the pgm and lat bits are cleared simultaneously, and an inter- rupt is generated if the ie bit is set. the data eep- rom interrupt request is cleared by hardware when the data eeprom interrupt vector is fetched. note : care should be taken during the program- ming cycle. writing to the same memory location will over-program the memory (logical and be- tween the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the fa lling edge of lat bit. it is not possible to read the latched data. this note is ilustrated by the figure 9 . figure 8. data eeprom programming flowchart read mode lat=0 pgm=0 write mode lat=1 pgm=0 read bytes in eeprom area writeupto16bytes in eeprom area (with the same 11 msb of the address) start programming cycle lat=1 pgm=1 (set by software) lat interrupt generation if ie=1 0 1 cleared by hardware st72334j/n, st72314j/n, st72124j 20/153 data eeprom (contd) 6.4 power saving modes wait mode the data eeprom can enter wait mode on ex- ecution of the wfi instruction of the microcontrol- ler. the data eeprom will immediately enter this mode if there is no programming in progress, otherwise the data eeprom will finish the cycle and then enter wait mode. halt mode the data eeprom immediatly enters halt mode if the microcontroller executes the halt in- struction. therefore the eeprom will stop the function in progress, and data may be corrupted. 6.5 access error handling if a read access occurs while lat=1, then the data bus will not be driven. if a write access occurs while lat=0, then the data on the bus will not be latched. if a programming cycle is interrupted (by software/ reset action), the memory data will not be guar- anteed. figure 9. data eeprom programming cycle lat erase cycle write cycle pgm t prog read operation not possible write of data latches read operation possible internal programming voltage eeprom interrupt st72334j/n, st72314j/n, st72124j 21/153 data eeprom (contd) 6.6 register description control/status register (csr) read/write reset value: 0000 0000 (00h) bit 7:3 = reserved, forced by hardware to 0. bit 2 = ie interrupt enable this bit is set and cleared by software. it enables the data eeprom interrupt capability when the pgm bit is cleared by hardware. the interrupt request is automatically cleared when the software enters the interrupt routine. 0: interrupt disabled 1: interrupt enabled bit 1 = lat latch access transfer this bit is set by software. it is cleared by hard- ware at the end of the programming cycle. it can only be cleared by software if pgm bit is cleared. 0: read mode 1: write mode bit 0 = pgm programming control and status this bit is set by software to begin the programming cycle. at the end of the programming cycle, this bit is cleared by hardware and an interrupt is generated if the ite bit is set. 0: programming finished or not yet started 1: programming cycle is in progress note : if the pgm bit is cleared during the program- ming cycle, the memory data is not guaranteed 70 00000ielatpgm st72334j/n, st72314j/n, st72124j 22/153 7 data eeprom register map and reset values 7.1 read-out protection option the data eeprom can be optionally read-out protected in st72334 rom devices (see option list on page 146 ). st72c334 flash devices do not have this protection option. address (hex.) register label 76543210 002ch eecsr reset value 00000 ie 0 rwm 0 pgm 0 st72334j/n, st72314j/n, st72124j 23/153 8 central processing unit 8.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 8.2 main features n 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes n two 8-bit index registers n 16-bit stack pointer n low power modes n maskable hardware interrupts n non-maskable software interrupt 8.3 cpu registers the 6 cpu registers shown in figure 10 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in- struction (pre) to indicate that the following in- struction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 10. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value st72334j/n, st72314j/n, st72124j 24/153 cpu registers (contd) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 3 = i interrupt mask . this bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in- structions and is tested by the jrm and jrnm in- structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptable because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the bit test and branch, shift and rotate instructions. 70 111hinzc st72334j/n, st72314j/n, st72124j 25/153 central processing unit (contd) stack pointer (sp) read/write reset value: 01 ffh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 11 ). since the stack is 256 bytes deep, the 8th most significant bits are forced by hardware. following an mcu reset, or after a reset stack pointer in- struction (rsp), the stack pointer contains its re- set value (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 11 . C when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. C on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 11. stack manipulation example 15 8 00000001 70 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h st72334j/n, st72314j/n, st72124j 26/153 9 supply, reset and clock management the st72334j/n, st72314j/n and st72124j mi- crocontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. an overview is shown in figure 12 . see section 16 "electrical characteris- tics" on page 107 for more details. main features n supply manager with main supply low voltage detection (lvd) n reset sequence manager (rsm) n multi-oscillator (mo) C 4 crystal/ceramic resonator oscillators C 1 external rc oscillator C 1 internal rc oscillator n clock security system (css) Cclock filter C backup safe oscillator figure 12. clock, reset and supply block diagram ie d 0 0 0 0 rf rf crsr css wdg f osc css interrupt lvd low voltage detector (lvd) multi- oscillator (mo) from watchdog peripheral osc1 reset vdd vss reset sequence manager (rsm) clock filter safe osc clock security system (css) osc2 to main clock controller st72334j/n, st72314j/n, st72124j 27/153 9.1 low voltage detector (lvd) to allow the integration of power management features in the application, the low voltage detec- tor function (lvd) generates a static reset when the v dd supply voltage is below a v it- reference value. this means that it secures the power-up as well as the power-down keeping the st7 in reset. the v it- reference value for a voltage drop is lower than the v it+ reference value for power-on in order to avoid a parasitic reset when the mcu starts run- ning and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: Cv it+ when v dd is rising Cv it- when v dd is falling the lvd function is illustrated in the figure 13 . provided the minimum v dd value (guaranteed for the oscillator frequency) is above v it- , the mcu can only be in two modes: C under full software control C in static safe reset in these conditions, secure operation is always en- sured for the application without the need for ex- ternal reset hardware. during a low voltage detector reset, the r eset pin is held low, thus permitting the mcu to reset other devices. notes : 1. the lvd allows the device to be used without any external reset circuitry. 2. three different reference levels are selectable through the option byte according to the applica- tion requirement. lvd application note application software can detect a reset caused by the lvd by reading the lvdrf bit in the crsr register. this bit is set by hardware when a lvd reset is generated and cleared by software (writing zero). figure 13. low voltage detector vs reset v dd v it+ reset v it- v hyst st72334j/n, st72314j/n, st72124j 28/153 9.2 reset sequence manager (rsm) 9.2.1 introduction the reset sequence manager includes three re- set sources as shown in figure 15 : n external reset source pulse n internal lvd reset (low voltage detection) n internal watchdog reset these sources act on the reset pin and it is al- ways kept low during the delay phase. the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 14 : n delay depending on the reset source n 4096 cpu clock cycle delay n reset vector fetch the 4096 cpu clock cycle delay allows the oscil- lator to stabilise and ensures that recovery has taken place from the reset state. the reset vector fetch phase duration is 2 clock cycles. figure 14. reset sequence phases figure 15. reset block diagram reset delay internal reset 4096 clock cycles fetch vector f cpu counter reset r on v dd watchdog reset lvd reset internal reset st72334j/n, st72314j/n, st72124j 29/153 reset sequence manager (contd) 9.2.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see electrical characteristics section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized. this detection is asynchro- nous and therefore the mcu can enter reset state even in halt mode. the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. two reset s equences can be associated with this reset source: short or long external reset pulse (see figure 16 ). starting from the external reset pulse recogni- tion, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . 9.2.3 internal low voltage detection reset two different reset s equences caused by the in- ternal lvd circuitry can be distinguished: n power-on reset n voltage drop r eset the device reset pin acts as an output that is pulled low when v dd st72334j/n, st72314j/n, st72124j 31/153 9.4 clock security system (css) the clock security system (css) protects the st7 against main clock problems. to allow the in- tegration of the security features in the applica- tions, it is based on a clock filter control and an in- ternal safe oscillator. the css can be enabled or disabled by option byte. 9.4.1 clock filter control the clock filter is based on a clock frequency limi- tation function. this filter function is able to detect and filter high frequency spikes on the st7 main clock. if the oscillator is not working properly (e.g. work- ing at a harmonic frequency of the resonator), the current active oscillator clock can be totally fil- tered, and then no clock signal is available for the st7 from this oscillator anymore. if the original clock source recovers, the filtering is stopped au- tomatically and the oscillator supplies the st7 clock. 9.4.2 safe oscillator control the safe oscillator of the css block is a low fre- quency back-up clock source (see figure 17 ). if the clock signal disappears (due to a broken or disconnected resonator...) during a safe oscillator period, the safe oscillator delivers a low frequency clock signal which allows the st7 to perform some rescue operations. automatically, the st7 clock source switches back from the safe oscillator if the original clock source recovers. limitation detection the automatic safe oscillator selection is notified by hardware setting the cssd bit of the crsr register. an interrupt can be generated if the cs- sie bit has been previously set. these two bits are described in the crsr register description. 9.4.3 low power modes 9.4.4 interrupts the css interrupt event generates an interrupt if the corresponding enable control bit (cssie) is set and the interrupt mask in the cc register is re- set (rim instruction). note 1: this interrupt allows to exit from active-halt mode if this mode is available in the mcu. figure 17. clock filter function and safe oscillator function mode description wait no effect on css. css interrupt cause the device to exit from wait mode. halt the crsr register is frozen. the css (in- cluding the safe oscillator) is disabled until halt mode is exited. the previous css configuration resumes when the mcu is woken up by an interrupt with exit from halt mode capability or from the counter reset value when the mcu is woken up by a reset. interrupt event event flag enable control bit exit from wait exit from halt 1) css event detection (safe oscillator acti- vated as main clock) cssd cssie yes no f osc /2 f cpu f osc /2 f cpu f sfosc safe oscillator function clock filter function st72334j/n, st72314j/n, st72124j 32/153 9.5 supply, reset and clock register description read/write reset value: 000x 000x (xxh) bit 7:5 = reserved , always read as 0. bit 4 = lvdrf lvd reset flag this bit indicates that the last reset was gener- ated by the lvd block. it is set by hardware (lvd reset) and cleared by software (writing zero). see wdgrf flag description for more details. when the lvd is disabled by option byte, the lvdrf bit value is undefined. bit 3 = reserved , always read as 0. bit 2 = cssie clock security syst . interrupt enable this bit enables the interrupt when a disturbance is detected by the clock security system (cssd bit set). it is set and cleared by software. 0: clock security system interrupt disabled 1: clock security system interrupt enabled refer to table 5, interrupt mapping, on page 34 for more details on the css interrupt vector. when the css is disabled by option byte, the cssie bit has no effect. bit 1 = cssd clock security system detection this bit indicates that the safe oscillator of the clock security system block has been selected by hardware due to a disturbance on the main clock signal (f osc ). it is set by hardware and cleared by reading the crsr register when the original oscil- lator recovers. 0: safe oscillator is not active 1: safe oscillator has been activated when the css is disabled by option byte, the cssd bit value is forced to 0. bit 0 = wdgrf watchdog reset flag this bit indicates that the last reset was gener- ated by the watchdog peripheral. it is set by hard- ware (watchdog reset) and cleared by software (writing zero) or an lvd reset (to ensure a sta- ble cleared state of the wdgrf flag when the cpu starts). combined with the lvdrf flag information, the flag description is given by the following table. application notes the lvdrf flag is not cleared when another re- set type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the origi- nal failure. in this case, a watchdog reset can be detected by software while an external reset can not. table 4. clock, reset and supply register map and reset values 70 000 lvd rf 0 css ie css d wdg rf reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lvd 1 x address (hex.) register label 76543210 002bh crsr reset value 0 0 0 lvdrf x0 cfie 0 cssd 0 wdgrf x st72334j/n, st72314j/n, st72124j 33/153 10 interrupts the st7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the interrupt mapping table and a non- maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 18 . the maskable interrupts must be enabled by clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). note: after reset, all interrupts are disabled. when an interrupt has to be serviced: C normal processing is suspended at the end of the current instruction execution. C the pc, x, a and cc registers are saved onto the stack. C the i bit of the cc register is set to prevent addi- tional interrupts. C the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the interrupt mapping table for vector address- es). the interrupt service routine should finish with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit will be cleared and the main program will resume. priority management by default, a servicing interrupt cannot be inter- rupted because the i bit is set by hardware enter- ing in interrupt routine. in the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the interrupt map- ping table). interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specifi- cally mentioned interrupts allow the processor to leave the halt low power mode (refer to the exit from halt column in the interrupt mapping ta- ble). 10.1 non maskable software interrupt this interrupt is entered when the trap instruc- tion is executed regardless of the state of the i bit. it will be serviced according to the flowchart on figure 18 . 10.2 external interrupts external interrupt vectors can be loaded into the pc register if the corresponding external interrupt occurred and if the i bit is cleared. these interrupts allow the processor to leave the halt low power mode. the external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). an external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins, connected to the same inter- rupt vector, are configured as interrupts, their sig- nals are logically nanded before entering the edge/level detection block. caution: the type of sensitivity defined in the mis- cellaneous or interrupt register (if available) ap- plies to the ei source. in case of a nanded source (as described on the i/o ports section), a low level on an i/o pin configured as input with interrupt, masks the interrupt request even in case of rising- edge sensitivity. 10.3 peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: C the i bit of the cc register is cleared. C the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: C writing 0 to the corresponding bit in the status register or C access to the status register while the flag is set followed by a read or write of an associated reg- ister. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being en- abled) will therefore be lost if the clear sequence is executed. st72334j/n, st72314j/n, st72124j 34/153 interrupts (contd) figure 18. interrupt processing flowchart table 5. interrupt mapping note 1. valid for halt and active-halt modes except for the mcc/rtc or css interrupt source which exits from active-halt mode only. n source block description register label priority order exit from halt 1) address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 not used fffah-fffbh 1 mcc/rtc css main clock controller time base interrupt or clock security system interrupt mccsr crsr yes fff8h-fff9h 2 ei0 external interrupt port a3..0 n/a fff6h-fff7h 3 ei1 external interrupt port f2..0 fff4h-fff5h 4 ei2 external interrupt port b3..0 fff2h-fff3h 5 ei3 external interrupt port b7..4 fff0h-fff1h 6 not used ffeeh-ffefh 7 spi spi peripheral interrupts spisr no ffech-ffedh 8 timer a timer a peripheral interrupts tasr ffeah-ffebh 9 timer b timer b peripheral interrupts tbsr ffe8h-ffe9h 10 sci sci peripheral interrupts scisr ffe6h-ffe7h 11 data-eeprom data eeprom interrupt eecsr ffe4h-ffe5h 12 not used ffe2h-ffe3h 13 ffe0h-ffe1h i bit set? y n iret? y n from reset load pc from interrupt vector stack pc, x, a, cc set i bit fetch next instruction execute instruction this clears i bit by default restore pc, x, a, cc from stack interrupt y n pending? st72334j/n, st72314j/n, st72124j 35/153 11 power saving modes 11.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the st7 (see figure 19 ): slow, wait (slow wait), ac- tive halt and halt. after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f cpu ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instruction whose action depends on the oscillator status. figure 19. power saving mode transitions 11.2 slow mode this mode has two targets: C to reduce power consumption by decreasing the internal clock in the device, C to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by three bits in the miscr1 register: the sms bit which enables or disables slow mode and two cpx bits which select the internal slow frequency (f cpu ). in this mode, the oscillator frequency can be divid- ed by 4, 8, 16 or 32 instead of 2 in normal operat- ing mode. the cpu and peripherals are clocked at this lower frequency. note : slow-wait mode is activated when enter- ing the wait mode while the device is already in slow mode. figure 20. slow mode clock transitions power consumption wait slow run active halt high low slow wait halt 00 01 sms cp1:0 f cpu new slow normal run mode miscr1 frequency request request f osc /2 f osc /4 f osc /8 f osc /2 st72334j/n, st72314j/n, st72124j 36/153 power saving modes (contd) 11.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the wfi instruction. all peripherals remain active. during wait mode, the i bit of the cc register is cleared, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the pro- gram counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 21 . figure 21. wait mode flow-chart note: 1. before servicing an interrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals i bit on on 0 off fetch reset vector or service interrupt cpu oscillator peripherals i bit on off 0 on cpu oscillator peripherals i bit on on x 1) on 4096 cpu clock cycle delay st72334j/n, st72314j/n, st72124j 37/153 power saving modes (contd) 11.4 active-halt and halt modes active-halt and halt modes are the two low- est power consumption modes of the mcu. they are both entered by executing the halt instruc- tion. the decision to enter either in active-halt or halt mode is given by the mcc/rtc interrupt enable flag (oie bit in mccsr register). 11.4.1 active-halt mode active-halt mode is the lowest power con- sumption mode of the mcu with a real time clock available. it is entered by executing the halt in- struction when the oie bit of the main clock con- troller status register (mccsr) is set (see section 14.2 "main clock controller with real time clock timer (mcc/rtc)" on page 52 for more details on the mccsr register). the mcu can exit active-halt mode on recep- tion of either an mcc/rtc interrupt, a specific in- terrupt (see table 5, interrupt mapping, on page 34 ) or a reset. when exiting active- halt mode by means of a reset or an interrupt, a 4096 cpu cycle delay occurs. after the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 23 ). when entering active-halt mode, the i bit in the cc register is cleared to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in active-halt mode, only the main oscillator and its associated counter (mcc/rtc) are run- ning to keep a wake-up time base. all other periph- erals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). the safeguard against staying locked in active- halt mode is provided by the oscillator interrupt. note: as soon as the interrupt capability of one of the oscillators is selected (mccsr.oie bit set), entering active-halt mode while the watchdog is active does not generate a reset. this means that the device cannot spend more than a defined delay in this power saving mode. figure 22. active-halt timing overview figure 23. active-halt mode flow-chart notes: 1. peripheral clocked with an external clock source can still be active. 2. only the mcc/rtc interrupt and some specific interrupts can exit the mcu from active-halt mode (such as external interrupt). refer to table 5, interrupt mapping, on page 34 for more details. 3. before servicing an interrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. mccsr oie bit power saving mode entered when halt instruction is executed 0 halt mode 1 active-halt mode halt run run 4096 cpu cycle delay reset or interrupt halt instruction fetch vector active [mccsr.oie=1] halt instruction reset interrupt 2) y n n y cpu oscillator peripherals 1) i bit on off 0 off fetch reset vector or service interrupt cpu oscillator peripherals 1) i bit on off x 3) on cpu oscillator peripherals i bits on on x 3) on 4096 cpu clock cycle delay (mccsr.oie=1) st72334j/n, st72314j/n, st72124j 38/153 power saving modes (contd) 11.4.2 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the halt instruction when the oie bit of the main clock controller status register (mccsr) is cleared (see section 14.2 "main clock con- troller with real time clock timer (mcc/rtc)" on page 52 for more details on the mccsr register). the mcu can exit halt mode on reception of ei- ther a specific interrupt (see table 5, interrupt mapping, on page 34 ) or a reset. w hen exiting halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and the 4096 cpu cycle delay is used to stabilize the os- cillator. after the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 25 ). when entering halt mode, the i bit in the cc reg- ister is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes immedi- ately. in halt mode, the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla- tor). the compatibility of watchdog operation with halt mode is configured by the wdghalt op- tion bit of the option byte. the halt instruction when executed while the watchdog system is en- abled, can generate a watchdog reset (see section 18.1 on page 144 for more details). figure 24. halt timing overview figure 25. halt mode flow-chart notes: 1. wdghalt is an option bit. see option byte sec- tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). re- fer to table 5, interrupt mapping, on page 34 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. halt run run 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [mccsr.oie=0] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) i bit off off 0 off fetch reset vector or service interrupt cpu oscillator peripherals i bit on off x 4) on cpu oscillator peripherals i bits on on x 4) on 4096 cpu clock cycle delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 (mccsr.oie=0) st72334j/n, st72314j/n, st72124j 39/153 12 i/o ports 12.1 introduction the i/o ports offer different functional modes: C transfer of data through digital inputs and outputs and for specific pins: C external interrupt generation C alternate signal input/output for the on-chip pe- ripherals. an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 12.2 functional description each port has 2 main registers: C data register (dr) C data direction register (ddr) and one optional register: C option register (or) each i/o pin may be programmed using the corre- sponding register bits in the ddr and or regis- ters: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not pro- vide this register refer to the i/o port implementa- tion section). the generic i/o block diagram is shown in figure 26 12.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. notes : 1. writing the dr register modifies the latch value but does not affect the pin status. 2. when switching from input to output mode, the dr register has to be written first to drive the cor- rect level on the pin as soon as the port is config- ured as an output. 3. do not use read/modify/write instructions (bset or bres) to modify the dr register external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external inter- rupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the mis- cellaneous register. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see pinout description and interrupt section). if several input pins are se- lected simultaneously as interrupt source, these are logically nanded. for this reason if one of the interrupt pins is tied low, it masks the other ones. in case of a floating input with interrupt configura- tion, special care must be taken when changing the configuration (see figure 27 ). the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the miscellane- ous register must be modified. 12.2.2 output modes the output configuration is selected by setting the corresponding ddr register bit. in this case, writ- ing the dr register applies this digital value to the i/o pin through the latch. then reading the dr reg- ister returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. dr register value and output pin status: 12.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip periph- eral, the i/o pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digitally readable by addressing the dr register. note : input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. dr push-pull open-drain 0v ss vss 1v dd floating st72334j/n, st72314j/n, st72124j 40/153 i/o ports (contd) figure 26. i/o port general block diagram table 6. i/o port mode options legend : ni - not implemented off - implemented not activated on - implemented and activated note : the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ss is implemented to protect the de- vice against positive stress. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up configuration p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external source (ei x ) interrupt polarity selection cmos schmitt trigger register access st72334j/n, st72314j/n, st72124j 41/153 i/o ports (contd) table 7. i/o port configurations notes: 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read the alternate function output status. 2. when the i/o port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the dr register content. hardware configuration input 1) open-drain output 2) push-pull output 2) configuration pad v dd r pu external interrupt polarity data bus pull-up interrupt dr register access w r from other pins source (ei x ) selection dr register configuration alternate input not implemented in true open drain i/o ports analog input pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports st72334j/n, st72314j/n, st72124j 42/153 i/o ports (contd) caution : the alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the select- ed pin to the common analog rail which is connect- ed to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. 12.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific feature of the i/o port such as adc in- put or true open drain. switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 27 other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 27. interrupt i/o port state transitions the i/o port register configurations are summa- rized as follows. standard ports pa5:4, pc7:0, pd7:0, pe7:4, pe1:0, pf7:6, pf4 interrupt ports pa2:0, pb7:5, pb2:0, pf1:0 (with pull-up) pa3, pb4, pb3, pf2 (without pull-up) true open drain ports pa7:6 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or mode ddr or floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 floating interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr floating input 0 open drain (high sink ports) 1 st72334j/n, st72314j/n, st72124j 43/153 i/o ports (contd) 12.4 low power modes 12.5 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and the i-bit in the cc reg- ister is reset (rim instruction). table 8. port configuration mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx yes yes port pin name input output or = 0 or = 1 or = 0 or = 1 high-sink port a pa7:6 floating true open-drain yes pa5:4 floating pull-up open drain push-pull pa3 floating floating interrupt open drain push-pull no pa2:0 floating pull-up interrupt open drain push-pull port b pb4:3 floating floating interrupt open drain push-pull pb7:5, pb2:0 floating pull-up interrupt open drain push-pull port c pc7:4, pc1:0 floating pull-up open drain push-pull pc3:2 floating pull-up open drain push-pull yes port d pd7:0 floating pull-up open drain push-pull no port e pe7:4 floating pull-up open drain push-pull yes pe1:0 floating pull-up open drain push-pull no port f pf7:6 floating pull-up open drain push-pull yes pf4 floating pull-up open drain push-pull no pf2 floating floating interrupt open drain push-pull pf1:0 floating pull-up interrupt open drain push-pull st72334j/n, st72314j/n, st72124j 44/153 i/o ports (contd) 12.5.1 register description data register (dr) port x data register pxdr with x = a, b, c, d, e or f. read/write reset value: 0000 0000 (00h) bit 7:0 = d[7:0] data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. reading the dr register returns either the dr register latch content (pin configured as output) or the digital value applied to the i/o pin (pin configured as input). data direction register (ddr) port x data direction register pxddr with x = a, b, c, d, e or f. read/write reset value: 0000 0000 (00h) bit 7:0 = dd[7:0] data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bits is set and cleared by software. 0: input mode 1: output mode option register (or) port x option register pxor with x = a, b, c, d, e or f. read/write reset value: 0000 0000 (00h) bit 7:0 = o[7:0] option register 8 bits. for specific i/o pins, this register is not implement- ed. in this case the ddr register is enough to se- lect the i/o pin configuration. the or register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. each bit is set and cleared by software. input mode: 0: floating input 1: pull-up input with or without interrupt output mode: 0: output open drain (with p-buffer deactivated) 1: output push-pull 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 70 o7 o6 o5 o4 o3 o2 o1 o0 st72334j/n, st72314j/n, st72124j 45/153 i/o ports (contd) table 9. i/o port register map and reset values notes: 1) the bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value. address (hex.) register label 76543210 reset value of all io port registers 00000000 0000h padr msb lsb 0001h paddr 0002h paor 1) 0004h pcdr msb lsb 0005h pcddr 0006h pcor 0008h pbdr msb lsb 0009h pbddr 000ah pbor 1) 000ch pedr msb lsb 000dh peddr 000eh peor 1) 0010h pddr msb lsb 0011h pdddr 0012h pdor 1) 0014h pfdr msb lsb 0015h pfddr 0016h pfor st72334j/n, st72314j/n, st72124j 46/153 13 miscellaneous registers the miscellaneous registers allow control over several different features such as the external in- terrupts or the i/o alternate functions. 13.1 i/o port interrupt sensitivity the external interrupt sensitivity is controlled by the isxx bits of the miscr1 miscellaneous regis- ter. this control allows to have two fully independ- ent external interrupt source sensitivities. each external interrupt source can be generated on four different events on the pin: n falling edge n rising edge n falling and rising edge n falling edge and low level to guarantee correct functionality, the sensitivity bits in the miscr1 register must be modified only when the i bit of the cc register is set to 1 (inter- rupt masked). see i/o port register and miscella- neous register descriptions for more details on the programming. 13.2 i/o port alternate functions the miscr registers manage four i/o port miscel- laneous alternate functions: n main clock signal (f cpu ) output on pf0 n a beep signal output on pf1 (with 3 selectable audio frequencies) n spi pin configuration: Css pin internal control to use the pc7 i/o port function while the spi is active. these functions are described in detail in the sec- tion 13 "miscellaneous registers" on page 46 . figure 28. ext. interrupt sensitivity ei2 interrupt source is10 is11 miscr1 sensitivity control pb1 pb2 pb0 pb3 pb5 pb6 pb4 pb7 ei3 ei0 interrupt source is20 is21 miscr1 sensitivity control pa1 pa2 pa0 pa3 pf1 pf2 pf0 ei1 st72334j/n, st72314j/n, st72124j 47/153 miscellaneous registers (contd) 13.3 registers description miscellaneous register 1 (miscr1) read/write reset value: 0000 0000 (00h) bit 7:6 = is1[1:0] ei2 and ei3 sensitivity the interrupt sensitivity, defined using the is1[1:0] bits, is applied to the following external interrupts: ei2 (port b3..0) and ei3 (port b7..4). these 2 bits can be written only when the i bit of the cc register is set to 1 (interrupt disabled). bit 5 = mco main clock out selection this bit enables the mco alternate function on the i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f osc /2 on i/o port) note : to reduce power consumption, the mco function is not active in active-halt mode. bit 4:3 = is2[1:0] ei0 and ei1 sensitivity the interrupt sensitivity, defined using the is2[1:0] bits, is applied to the following external interrupts:- ei0 (port a3..0) and ei1 (port f2..0). these 2 bits can be written only when the i bit of the cc register is set to 1 (interrupt disabled). bit 2:1 = cp[1:0] cpu clock prescaler these bits select the cpu clock prescaler which is applied in the different slow modes. their action is conditioned by the setting of the sms bit. these two bits are set and cleared by software bit 0 = sms slow mode select this bit is set and cleared by software. 0: normal mode. f cpu = f osc / 2 1: slow mode. f cpu is given by cp1, cp0 see low power consumption mode and mcc chapters for more details. 70 is11 is10 mco is21 is20 cp1 cp0 sms external interrupt sensitivity is11 is10 falling edge & low level 0 0 rising edge only 0 1 falling edge only 1 0 rising and falling edge 1 1 f cpu in slow mode cp1 cp0 f osc / 4 0 0 f osc / 8 1 0 f osc / 16 0 1 f osc / 32 1 1 st72334j/n, st72314j/n, st72124j 48/153 miscellaneous registers (contd) miscellaneous register 2 (miscr2) read/write reset value: 0000 0000 (00h) bit 7:6 = reserved must always be cleared bit 5:4 = bc[1:0] beep control these 2 bits select the pf1 pin beep capability. the beep output signal is available in active- halt mode but has to be disabled to reduce the consumption. bit 3:2 = reserved must always be cleared bit 1 = ssm ss mode selection it is set and cleared by software. 0: normal mode - ss uses information coming from the ss pin of the spi. 1: i/o mode, the spi uses the information stored into bit ssi. bit 0 = ssi ss internal mode this bit replaces pin ss of the spi when bit ssm is set to 1. (see spi description). it is set and cleared by software. table 10. miscellaneous register map and reset values 70 - - bc1 bc0 - - ssm ssi beep mode with f osc =16mhz bc1 bc0 off 0 0 ~2-khz output beep signal ~50% duty cycle 01 ~1-khz 1 0 ~500-hz 1 1 address (hex.) register label 76543210 0020h miscr1 reset value is11 0 is10 0 mco 0 is21 0 is20 0 cp1 0 cp0 0 sms 0 0040h miscr2 reset value 0 0 bc1 0 bc0 000 ssm 0 ssi 0 st72334j/n, st72314j/n, st72124j 49/153 14 on-chip peripherals 14.1 watchdog timer (wdg) 14.1.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counters contents before the t6 bit be- comes cleared. 14.1.2 main features n programmable timer (64 increments of 12288 cpu cycles) n programmable reset n reset (if watchdog activated) after a halt instruction or when the t6 bit reaches zero n hardware watchdog selectable by option byte n watchdog reset indicated by status flag (in versions with safe reset option only) 14.1.3 functional description the counter value stored in the cr register (bits t[6:0]), is decremented every 12,288 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. figure 29. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) ? 12288 t1 t2 t3 t4 t5 st72334j/n, st72314j/n, st72124j 50/153 watchdog timer (contd) the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the cr register must be between ffh and c0h (see table 11 .watchdog timing (fcpu = 8 mhz) ): C the wdga bit is set (watchdog enabled) C the t6 bit is set to prevent generating an imme- diate reset C the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. table 11.watchdog timing (f cpu = 8 mhz) notes: following a reset, the watchdog is disa- bled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. 14.1.4 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. refer to the device-specific option byte descrip- tion. 14.1.5 low power modes 14.1.6 interrupts none. 14.1.7 register description control register (cr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch- dog option is enabled by option byte. bit 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). status register (sr) read/write reset value*: 0000 0000 (00h) bit 0 = wdogf watchdog flag . this bit is set by a watchdog reset and cleared by software or a power on/off reset. this bit is useful for distinguishing power/on off or external reset and watchdog reset. 0: no watchdog reset occurred 1: watchdog reset occurred * only by software and power on/off reset note: this register is not used in versions without lvd reset. cr register initial value wdg timeout period (ms) max ffh 98.304 min c0h 1.536 mode description wait no effect on watchdog. halt immediate reset generation as soon as the halt instruction is executed if the watchdog is activated (wdga bit is set). 70 wdga t6 t5 t4 t3 t2 t1 t0 70 - ------wdogf st72334j/n, st72314j/n, st72124j 51/153 watchdog timer (contd) table 12. watchdog timer register map and reset values address (hex.) register label 76543210 002ah wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 st72334j/n, st72314j/n, st72124j 52/153 14.2 main clock controller with real time clock timer (mcc/rtc) the main clock controller consists of three differ- ent functions: n a programmable cpu clock prescaler n a clock-out signal to supply external devices n a real time clock timer with interrupt capability each function can be used independently and si- multaneously. 14.2.1 programmable cpu clock prescaler the programmable cpu clock prescaler supplies the clock for the st7 cpu and its internal periph- erals. it manages slow power saving mode (see section 11.2 "slow mode" on page 35 for more details). the prescaler selects the f cpu main clock frequen- cy and is controlled by three bits in the miscr1 register: cp[1:0] and sms. caution : the prescaler does not act on the can peripheral clock source. this peripheral is always supplied by the f osc /2 clock source. 14.2.2 clock-out capability the clock-out capability is an alternate function of an i/o port pin that outputs a f osc /2 clock to drive external devices. it is controlled by the mco bit in the miscr1 register. caution : when selected, the clock out pin sus- pends the clock during active-halt mode. 14.2.3 real time clock timer (rtc) the counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. four different time bases depend- ing directly on f osc are available. the whole func- tionality is controlled by four bits of the mccsr register: tb[1:0], oie and oif. when the rtc interrupt is enabled (oie bit set), the st7 enters active-halt mode when the halt instruction is executed. see section 11.4 "active-halt and halt modes" on page 37 for more details. figure 30. main clock controller (mcc/rtc) block diagram div 2, 4, 8, 16 mcc/rtc interrupt div 2 sms cp1 cp0 tb1 tb0 oie oif cpu clock miscr1 rtc counter to cpu and peripherals f osc f cpu mco port function alternate mco - - - - 0 0 0 0 mccsr f osc /2 st72334j/n, st72314j/n, st72124j 53/153 main clock controller with real time clock timer (contd) miscellaneous register 1 (miscr1) see section 13 on page 46 . main clock control/status register (mccsr) read/write reset value: 0000 0001 (01h) bit 7:4 = reserved, always read as 0. bit 3:2 = tb[1:0] time base control these bits select the programmable divider time base. they are set and cleared by software. a modification of the time base is taken into ac- count at the end of the current period (previously set) to avoid unwanted time shift. this allows to use this time base as a real time clock. bit 1 = oie oscillator interrupt enable this bit set and cleared by software. 0: oscillator interrupt disabled 1: oscillator interrupt enabled this interrupt allows to exit from active-halt mode. when this bit is set, calling the st7 software halt instruction enters the active-halt power saving mode . bit 0 = oif oscillator interrupt flag this bit is set by hardware and cleared by software reading the csr register. it indicates when set that the main oscillator has measured the selected elapsed time (tb1:0). 0: timeout not reached 1: timeout reached caution : the bres and bset instructions must not be used on the mccsr register to avoid unintentionally clearing the oif bit. 14.2.4 low power modes 14.2.5 interrupts the mcc/rtc interrupt event generates an inter- rupt if the oie bit of the mccsr register is set and the interrupt mask in the cc register is not active (rim instruction). note : 1. the mcc/rtc interrupt allows to exit from ac- tive-halt mode, not from halt mode. table 13. mcc register map and reset values 70 0000tb1tb0oieoif counter prescaler time base tb1 tb0 f osc =8mhz f osc =16mhz 32000 4ms 2ms 0 0 64000 8ms 4ms 0 1 160000 20ms 10ms 1 0 400000 50ms 25ms 1 1 mode description wait no effect on mcc/rtc peripheral. mcc/rtc interrupt cause the device to exit from wait mode. active- halt no effect on mcc/rtc counter (oie bit is set), the registers are frozen. mcc/rtc interrupt cause the device to exit from active-halt mode. halt mcc/rtc counter and registers are frozen. mcc/rtc operation resumes when the mcu is woken up by an interrupt with exit from halt capability. interrupt event event flag enable control bit exit from wait exit from halt time base overflow event oif oie yes no 1) address (hex.) register label 76543210 0029h mccsr reset value 0 0 0 0 tb1 0 tb0 0 oie 0 oif 1 st72334j/n, st72314j/n, st72124j 54/153 14.3 16-bit timer 14.3.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including measuring the pulse lengths of up to two input sig- nals ( input capture ) or generating up to two output waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a mcu reset as long as the timer clock frequen- cies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 14.3.2 main features n programmable prescaler: f cpu divided by 2, 4 or 8. n overflow status flag and maskable interrupt n external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge n output compare functions with: C 2 dedicated 16-bit registers C 2 dedicated programmable signals C 2 dedicated status flags C 1 dedicated maskable interrupt n input capture functions with: C 2 dedicated 16-bit registers C 2 dedicated active edge selection signals C 2 dedicated status flags C 1 dedicated maskable interrupt n pulse width modulation mode (pwm) n one pulse mode n 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk)* the block diagram is shown in figure 31 . *note: some timer pins may not be available (not bonded) in some st7 devices. refer to the device pin out description. when reading an input signal on a non-bonded pin, the value will always be 1. 14.3.3 functional description 14.3.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high & low. counter register (cr): C counter high register (chr) is the most sig- nificant byte (ms byte). C counter low register (clr) is the least sig- nificant byte (ls byte). alternate counter register (acr) C alternate counter high register (achr) is the most significant byte (ms byte). C alternate counter low register (aclr) is the least significant byte (ls byte). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register (sr). (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit tim- er). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 14 clock control bits . the value in the counter register re- peats every 131072, 262144 or 524288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency. st72334j/n, st72314j/n, st72124j 55/153 16-bit timer (contd) figure 31. timer block diagram mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 0 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (status register) sr 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register note: if ic, oc and to interrupt requests have separate vectors then the last or is not present (see device interrupt vector table) (see note) st72334j/n, st72314j/n, st72124j 56/153 16-bit timer (contd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, out- put compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: C the tof bit of the sr register is set. C a timer interrupt is generated if: C toie bit of the cr1 register is set and C i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. note: the tof bit is not cleared by accessing the aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 14.3.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in the cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the exter- nal clock pin extclk that will trigger the free run- ning counter. the counter is synchronised with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the cpu clock frequency. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + d t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte st72334j/n, st72314j/n, st72124j 57/153 16-bit timer (contd) figure 32. counter timing diagram, internal clock divided by 2 figure 33. counter timing diagram, internal clock divided by 4 figure 34. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high. when it is low, the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 st72334j/n, st72314j/n, st72124j 58/153 16-bit timer (contd) 14.3.3.3 input capture in this section, the index, i , may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition is detected by the icap i pin (see figure 5). the ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure: to use the input capture function, select the fol- lowing in the cr2 register: C select the timer clock (cc[1:0]) (see table 14 clock control bits ). C select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). and select the following in the cr1 register: C set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin C select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). when an input capture occurs: C the icf i bit is set. C the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 36 ). C a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. notes: 1. after reading the ic i hr register, the transfer of input capture data is inhibited and icf i will never be set until the ic i lr register is also read. 2. the ic i r register contains the free running counter value which corresponds to the most recent input capture. 3. the 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. in one pulse mode and pwm mode only the input capture 2 function can be used. 5. the alternate inputs (icap1 & icap2) are always directly connected to the timer. so any transitions on these pins activate the input cap- ture function. moreover if one of the icap i pin is configured as an input and the second one as an output, an interrupt can be generated if the user tog- gles the output pin and if the icie bit is set. this can be avoided if the input capture func- tion i is disabled by reading the ic i hr (see note 1). 6. the tof bit can be used with an interrupt in order to measure events that exceed the timer range (ffffh). ms byte ls byte icir ic i hr ic i lr st72334j/n, st72314j/n, st72124j 59/153 16-bit timer (contd) figure 35. input capture block diagram figure 36. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: a ctive edge is rising edge. st72334j/n, st72314j/n, st72124j 60/153 16-bit timer (contd) 14.3.3.4 output compare in this section, the index, i , may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: C assigns pins with a programmable value if the oc i e bit is set C sets a flag in the status register C generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the fol- lowing in the cr2 register: C set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. C select the timer clock (cc[1:0]) (see table 14 clock control bits ). and select the following in the cr1 register: C select the olvl i bit to applied to the ocmp i pins after the match occurs. C set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: C ocf i bit is set. C the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). C a timer interrupt is generated if the ocie bit is set in the cr1 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: d t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 de- pending on cc[1:0] bits, see table 14 clock control bits ) if the timer clock is an external clock, the formula is: where: d t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (i.e. clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: C write to the oc i hr register (further compares are inhibited). C read the sr register (first step of the clearance of the ocf i bit, which may be already set). C write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr d oc i r = d t * f cpu presc d oc i r = d t * f ext st72334j/n, st72314j/n, st72124j 61/153 16-bit timer (contd) notes: 1. after a processor write cycle to the oc i hr reg- ister, the output compare function is inhibited until the oc i lr register is also written. 2. if the oc i e bit is not set, the ocmp i pin is a general i/o port and the olvl i bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3. when the timer clock is f cpu /2, ocf i and ocmp i are set while the counter value equals the oc i r register value (see figure 38 on page 62 ). this behaviour is the same in opm or pwm mode. when the timer clock is f cpu /4, f cpu /8 or in external clock mode, ocf i and ocmp i are set while the counter value equals the oc i r regis- ter value plus 1 (see figure 39 on page 62 ). 4. the output compare functions can be used both for generating external events on the ocmp i pins even if the input capture mode is also used. 5. the value in the 16-bit oc i r register and the olv i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new elapsed timeout. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. folvl i bits have no effect in either one-pulse mode or pwm mode. figure 37. output compare block diagram output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1 st72334j/n, st72314j/n, st72124j 62/153 16-bit timer (contd) figure 38. output compare timing diagram, f timer =f cpu /2 figure 39. output compare timing diagram, f timer =f cpu /4 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output compare flag i (ocf i ) st72334j/n, st72314j/n, st72124j 63/153 16-bit timer (contd) 14.3.3.5 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure: to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. select the following in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. C select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: C set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. C set the opm bit. C select the timer clock cc[1:0] (see table 14 clock control bits ). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffch and the olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the value fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. the oc1r register value required for a specific timing application can be calculated using the fol- lowing formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on the cc[1:0] bits, see table 14 clock control bits ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin (see figure 40 ). notes: 1. the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. 4. the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5. when one pulse mode is used oc1r is dedi- cated to this mode. nevertheless oc2r and ocf2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the olvl2 level is dedi- cated to one pulse mode. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 st72334j/n, st72314j/n, st72124j 64/153 16-bit timer (contd) figure 40. one pulse mode timing example figure 41. pulse width modulation mode timing example counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1 fffc fffd fffe 2ed0 2ed1 2ed2 st72334j/n, st72314j/n, st72124j 65/153 16-bit timer (contd) 14.3.3.6 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. the pulse width modulation mode uses the com- plete output compare 1 function plus the oc2r register, and so these functions cannot be used when the pwm mode is activated. procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corre- sponding to the period of the pulse if olvl1=0 and olvl2=1, using the formula in the oppo- site column. 3. select the following in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc1r register. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: C set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. C set the pwm bit. C select the timer clock (cc[1:0]) (see table 14 clock control bits ). if olvl1=1 and olvl2=0, the length of the posi- tive pulse is the difference between the oc2r and oc1r registers. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on cc[1:0] bits, see table 14 clock control bits ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 41 ) notes: 1. after a write instruction to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. 2. the ocf1 and ocf2 bits cannot be set by hardware in pwm mode, therefore the output compare interrupt is inhibited. 3. the icf1 bit is set by hardware when the coun- ter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4. in pwm mode the icap1 pin can not be used to perform input capture because it is discon- nected from the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset after each period and icf1 can also generate an interrupt if icie is set. 5. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 st72334j/n, st72314j/n, st72124j 66/153 16-bit timer (contd) 14.3.4 low power modes 14.3.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chap- ter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 14.3.6 summary of timer modes 1) see note 4 in section 14.3.3.5 "one pulse mode" on page 63 2) see note 5 in section 14.3.3.5 "one pulse mode" on page 63 3) see note 4 in section 14.3.3.6 "pulse width modulation mode" on page 65 mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the mcu is woken up by an interrupt with exit from halt mode capability or from the counter reset value when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequent- ly, when the mcu is woken up by an interrupt with exit from halt mode capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie yes no input capture 2 event icf2 yes no output compare 1 event (not available in pwm mode) ocf1 ocie yes no output compare 2 event (not available in pwm mode) ocf2 yes no timer overflow event tof toie yes no modes available resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) yes yes yes yes output compare (1 and/or 2) yes yes yes yes one pulse mode no not recommended 1) no partially 2) pwm mode no not recommended 3) no no st72334j/n, st72314j/n, st72124j 67/153 16-bit timer (contd) 14.3.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no suc- cessful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 st72334j/n, st72314j/n, st72124j 68/153 16-bit timer (contd) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output com- pare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the internal output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output com- pare mode). whatever the value of the oc2e bit, the internal output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bits 3:2 = cc[1:0] clock control. the timer clock mode depends on these bits: table 14. clock control bits note : if the external clock pin is not available, pro- gramming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin (extclk) will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 0 1 f cpu / 8 1 0 external clock (where available) 11 st72334j/n, st72314j/n, st72124j 69/153 16-bit timer (contd) status register (sr) read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter matches the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) register. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter has rolled over from ffffh to 0000h. to clear this bit, first read the sr register, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter matches the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) register. bit 2-0 = reserved, forced by hardware to 0. input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 icf1 ocf1 tof icf2 ocf2 0 0 0 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb st72334j/n, st72314j/n, st72124j 70/153 16-bit timer (contd) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in sr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb st72334j/n, st72314j/n, st72124j 71/153 16-bit timer (contd) table 15. 16-bit timer register map and reset values address (hex.) register label 76543210 timer a: 32 timer b: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer a: 31 timer b: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer a: 33 timer b: 43 sr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 - 0 - 0 - 0 timer a: 34 timer b: 44 ichr1 reset value msb - ------ lsb - timer a: 35 timer b: 45 iclr1 reset value msb - ------ lsb - timer a: 36 timer b: 46 ochr1 reset value msb - ------ lsb - timer a: 37 timer b: 47 oclr1 reset value msb - ------ lsb - timer a: 3e timer b: 4e ochr2 reset value msb - ------ lsb - timer a: 3f timer b: 4f oclr2 reset value msb - ------ lsb - timer a: 38 timer b: 48 chr reset value msb 1111111 lsb 1 timer a: 39 timer b: 49 clr reset value msb 1111110 lsb 0 timer a: 3a timer b: 4a achr reset value msb 1111111 lsb 1 timer a: 3b timer b: 4b aclr reset value msb 1111110 lsb 0 timer a: 3c timer b: 4c ichr2 reset value msb - ------ lsb - timer a: 3d timer b: 4d iclr2 reset value msb - ------ lsb - st72334j/n, st72314j/n, st72124j 72/153 14.4 serial peripheral interface (spi) 14.4.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. the spi is normally used for communication be- tween the microcontroller and external peripherals or another microcontroller. refer to the pin description chapter for the device- specific pin-out. 14.4.2 main features n full duplex, three-wire synchronous transfers n master or slave operation n four master mode frequencies n maximum slave mode frequency = f cpu /4. n four programmable master bit rates n programmable clock polarity and phase n end of transfer interrupt flag n write collision flag protection n master mode fault protection capability. 14.4.3 general description the spi is connected to external devices through 4 alternate pins: C miso: master in slave out pin C mosi: master out slave in pin C sck: serial clock pin Css : slave select pin a basic example of interconnections between a single master and a single slave is illustrated on figure 42 . the mosi pins are connected together as are miso pins. in this way data is transferred serially between master and slave (most significant bit first). when the master device transmits data to a slave device via mosi pin, the slave device responds by sending data to the master device via the miso pin. this implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master de- vice via the sck pin). thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. a status flag is used to indicate that the i/o operation is com- plete. four possible data/clock timing relationships may be chosen (see figure 45 ) but master and slave must be programmed with the same timing mode. figure 42. serial peripheral interface master/slave 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit st72334j/n, st72314j/n, st72124j 73/153 serial peripheral interface (contd) figure 43. serial peripheral interface block diagram dr read buffer 8-bit shift register write read internal bus spi spie spe spr2 mstr cpha spr0 spr1 cpol spif wcol modf serial clock generator mosi miso ss sck control state cr sr - ---- it request master control st72334j/n, st72314j/n, st72124j 74/153 serial peripheral interface (contd) 14.4.4 functional description figure 42 shows the serial peripheral interface (spi) block diagram. this interface contains 3 dedicated registers: C a control register (cr) C a status register (sr) C a data register (dr) refer to the cr, sr and dr registers in section 14.4.7 for the bit definitions. 14.4.4.1 master configuration in a master configuration, the serial clock is gener- ated on the sck pin. procedure C select the spr0 & spr1 bits to define the se- rial clock baud rate (see cr register). C select the cpol and cpha bits to define one of the four relationships between the data transfer and the serial clock (see figure 45 ). Cthe ss pin must be connected to a high level signal during the complete byte transmit se- quence. C the mstr and spe bits must be set (they re- main set only if the ss pin is connected to a high level signal). in this configuration the mosi pin is a data output and to the miso pin is a data input. transmit sequence the transmit sequence begins when a byte is writ- ten the dr register. the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: C the spif bit is set by hardware C an interrupt is generated if the spie bit is set and the i bit in the ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set 2. a read to the dr register. note: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read. st72334j/n, st72314j/n, st72124j 75/153 serial peripheral interface (contd) 14.4.4.2 slave configuration in slave configuration, the serial clock is received on the sck pin from the master device. the value of the spr0 & spr1 bits is not used for the data transfer. procedure C for correct data transfer, the slave device must be in the same timing mode as the mas- ter device (cpol and cpha bits). see figure 45 . Cthe ss pin must be connected to a low level signal during the complete byte transmit se- quence. C clear the mstr bit and set the spe bit to as- sign the pins to alternate function. in this configuration the mosi pin is a data input and the miso pin is a data output. transmit sequence the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: C the spif bit is set by hardware C an interrupt is generated if spie bit is set and i bit in ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set. 2.a read to the dr register. notes: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 14.4.4.6 ). depending on the cpha bit, the ss pin has to be set to write to the dr register between each data byte transfer to avoid a write collision (see section 14.4.4.4 ). st72334j/n, st72314j/n, st72124j 76/153 serial peripheral interface (contd) 14.4.4.3 data transfer format during an spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). the serial clock is used to syn- chronize the data transfer during a sequence of eight clock pulses. the ss pin allows individual selection of a slave device; the other slave devices that are not select- ed do not interfere with the spi transfer. clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits. the cpol (clock polarity) bit controls the steady state value of the clock when no data is being transferred. this bit affects both master and slave modes. the combination between the cpol and cpha (clock phase) bits selects the data capture clock edge. figure 45 , shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. the ss pin is the slave device select input and can be driven by the master device. the master device applies data to its mosi pin- clock edge before the capture clock edge. cpha bit is set the second edge on the sck pin (falling edge if the cpol bit is reset, rising edge if the cpol bit is set) is the msbit capture strobe. data is latched on the occurrence of the second clock transition. no write collision should occur even if the ss pin stays low during a transfer of several bytes (see figure 44 ). cpha bit is reset the first edge on the sck pin (falling edge if cpol bit is set, rising edge if cpol bit is reset) is the msbit capture strobe. data is latched on the oc- currence of the first clock transition. the ss pin must be toggled high and low between each byte transmitted (see figure 44 ). to protect the transmission from a write collision a low value on the ss pin of a slave device freezes the data in its dr register and does not allow it to be altered. therefore the ss pin must be high to write a new data byte in the dr without producing a write collision. figure 44. cpha / ss timing diagram mosi/miso master ss slave ss (cpha=0) slave ss (cpha=1) byte 1 byte 2 byte 3 vr02131a st72334j/n, st72314j/n, st72124j 77/153 serial peripheral interface (contd) figure 45. data clock timing diagram cpol = 1) cpol = 0) miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 cpol = 1 cpol = 0 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) vr02131b msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit sclk (with sclk (with st72334j/n, st72314j/n, st72124j 78/153 serial peripheral interface (contd) 14.4.4.4 write collision error a write collision occurs when the software tries to write to the dr register while a data transfer is tak- ing place with an external device. when this hap- pens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. in slave mode when the cpha bit is set: the slave device will receive a clock (sck) edge prior to the latch of the first data transfer. this first clock edge will freeze the data in the slave device dr register and output the msbit on to the exter- nal miso pin of the slave device. the ss pin low state enables the slave device but the output of the msbit onto the miso pin does not take place until the first data transfer clock edge. when the cpha bit is reset: data is latched on the occurrence of the first clock transition. the slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the dr register after its ss pin has been pulled low. for this reason, the ss pin must be high, between each data byte transfer, to allow the cpu to write in the dr register without generating a write colli- sion. in master mode collision in the master device is defined as a write of the dr register while the internal serial clock (sck) is in the process of transfer. the ss pin signal must be always high on the master device. wcol bit the wcol bit in the sr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 46 ). figure 46. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read sr read dr write dr 2nd step spif =0 wcol=0 spif =0 wcol=0 if no transfer has started wcol=1 if a transfer has started clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 before the 2nd step read sr read dr note: writing to the dr register instead of reading in it does not reset the wcol bit read sr or then then then st72334j/n, st72314j/n, st72124j 79/153 serial peripheral interface (contd) 14.4.4.5 master mode fault master mode fault occurs when the master device has its ss pin pulled low, then the modf bit is set. master mode fault affects the spi peripheral in the following ways: C the modf bit is set and an spi interrupt is generated if the spie bit is set. C the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. C the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read or write access to the sr register while the modf bit is set. 2. a write to the cr register. notes: to avoid any multiple slave conflicts in the case of a system comprising several mcus, the ss pin must be pulled high during the clearing se- quence of the modf bit. the spe and mstr bits may be restored to their original state during or af- ter this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device the modf bit can not be set, but in a multi master configuration the device can be in slave mode with this modf bit set. the modf bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine. 14.4.4.6 overrun condition an overrun condition occurs when the master de- vice has sent several data bytes and the slave de- vice has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the dr register returns this byte. all other bytes are lost. this condition is not detected by the spi peripher- al. st72334j/n, st72314j/n, st72124j 80/153 serial peripheral interface (contd) 14.4.4.7 single master and multimaster configurations there are two types of spi systems: C single master system C multimaster system single master system a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 47 ). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written its dr regis- ter. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multi-master system a multi-master system may also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the cr register and the modf bit in the sr register. figure 47. single master configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu st72334j/n, st72314j/n, st72124j 81/153 serial peripheral interface (contd) 14.4.5 low power modes 14.4.6 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi operation resumes when the mcu is woken up by an interrupt with exit from halt mode capability. interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes no master mode fault event modf yes no st72334j/n, st72314j/n, st72124j 82/153 serial peripheral interface (contd) 14.4.7 register description control register (cr) read/write reset value: 0000xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif=1 or modf=1 in the sr register bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 14.4.4.5 "master mode fault" on page 79 ). 0: i/o port connected to pins 1: spi alternate functions connected to pins the spe bit is cleared by reset, so the spi periph- eral is not initially connected to the external pins. bit 5 = spr2 divider enable . this bit is set and cleared by software and it is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 16 . 0: divider by 2 enabled 1: divider by 2 disabled bit 4 = mstr master. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 14.4.4.5 "master mode fault" on page 79 ). 0: slave mode is selected 1: master mode is selected, the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are re- versed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the steady state of the serial clock. the cpol bit affects both the master and slave modes. 0: the steady state is a low value at the sck pin. 1: the steady state is a high value at the sck pin. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. bit 1:0 = spr[1 : 0] serial peripheral rate. these bits are set and cleared by software.used with the spr2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. these 2 bits have no effect in slave mode. table 16. serial peripheral baud rate 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1 st72334j/n, st72314j/n, st72124j 83/153 serial peripheral interface (contd) status register (sr) read only reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag. this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the cr register. it is cleared by a soft- ware sequence (an access to the sr register fol- lowed by a read or write to the dr register). 0: data transfer is in progress or has been ap- proved by a clearing sequence. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is set, all writes to the dr register are inhibited. bit 6 = wcol write collision status. this bit is set by hardware when a write to the dr register is done during a transmit sequence. it is cleared by a software sequence (see figure 46 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = unused. bit 4 = modf mode fault flag. this bit is set by hardware when the ss pin is pulled low in master mode (see section 14.4.4.5 "master mode fault" on page 79 ). an spi interrupt can be generated if spie=1 in the cr register. this bit is cleared by a software sequence (an ac- cess to the sr register while modf=1 followed by a write to the cr register). 0: no master mode fault detected 1: a fault in master mode has been detected bits 3-0 = unused. data i/o register (dr) read/write reset value: undefined the dr register is used to transmit and receive data on the serial bus. in the master device only a write to this register will initiate transmission/re- ception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. warning: a write to the dr register places data directly into the shift register for transmission. a read to the the dr register returns the value lo- cated in the buffer and not the contents of the shift register (see figure 43 ). 70 spif wcol - modf - - - - 70 d7 d6 d5 d4 d3 d2 d1 d0 st72334j/n, st72314j/n, st72124j 84/153 serial peripheral interface (contd) table 17. spi register map and reset values address (hex.) register label 76543210 0021h spidr reset value msb xxxxxxx lsb x 0022h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0023h spisr reset value spif 0 wcol 00 modf 00000 st72334j/n, st72314j/n, st72124j 85/153 14.5 serial communications interface (sci) 14.5.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci offers a very wide range of baud rates using two baud rate generator systems. 14.5.2 main features n full duplex, asynchronous communications n nrz standard format (mark/space) n dual baud rate generator systems n independently programmable transmit and receive baud rates up to 250k baud using conventional baud rate generator and up to 500k baud using the extended baud rate generator. n programmable data word length (8 or 9 bits) n receive buffer full, transmit buffer empty and end of transmission flags n two receiver wake-up modes: C address bit (msb) C idle line n muting function for multiprocessor configurations n lin compatible (if mcu clock frequency tolerance 2%) n separate enable bits for transmitter and receiver n three error detection flags: C overrun error C noise error C frame error n five interrupt sources with flags: C transmit data register empty C transmission complete C receive data register full C idle line received C overrun error detected 14.5.3 general description the interface is externally connected to another device by two pins (see figure 2.): C tdo: transmit data output. when the transmit- ter is disabled, the output pin returns to its i/o port configuration. when the transmitter is ena- bled and nothing is to be transmitted, the tdo pin is at high level. C rdi: receive data input is the serial data input. oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. through this pins, serial data is transmitted and re- ceived as frames comprising: C an idle line prior to transmission or reception C a start bit C a data word (8 or 9 bits) least significant bit first C a stop bit indicating that the frame is complete. this interface uses two types of baud rate generator: C a conventional type for commonly-used baud rates, C an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies. 14.5.4 lin protocol support for lin applications where resynchronization is not required (application clock tolerance less than or equal to 2%) the lin protocol can be efficiently implemented with this standard sci. st72334j/n, st72314j/n, st72124j 86/153 serial communications interface (contd) figure 48. sci block diagram wake up unit receiver control sr transmit control tdre tc rdrf idle or nf fe - sci control interrupt cr1 r8 t8 - m wake - -- received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) dr transmitter clock receiver clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /2 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie cr2 st72334j/n, st72314j/n, st72124j 87/153 serial communications interface (contd) 14.5.5 functional description the block diagram of the serial control interface, is shown in figure 1.. it contains 6 dedicated reg- isters: C two control registers (cr1 & cr2) C a status register (sr) C a baud rate register (brr) C an extended prescaler receiver register (erpr) C an extended prescaler transmitter register (etpr) refer to the register descriptions in section 0.1.8 for the definitions of each bit. 14.5.5.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the cr1 register (see figure 1.). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of 1s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving 0s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an ex- tra 1 bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 49. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra 1 data frame break frame start bit extra 1 data frame next data frame next data frame st72334j/n, st72314j/n, st72124j 88/153 serial communications interface (contd) 14.5.5.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the cr1 reg- ister. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the dr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 1.). procedure C select the m bit to define the word length. C select the desired baud rate using the brr and the etpr registers. C set the te bit to assign the tdo pin to the alter- nate function and to send a idle frame as first transmission. C access the sr register and write the data to send in the dr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the sr register 2. a write to the dr register the tdre bit is set by hardware and it indicates: C the tdr register is empty. C the data transfer is beginning. C the next data can be written in the dr register without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write in- struction to the dr register stores the data in the tdr register and which is copied in the shift regis- ter at the end of the current transmission. when no transmission is taking place, a write in- struction to the dr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit or after the break frame) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the sr register 2. a write to the dr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit l oads the shift register with a break character. the break frame length depends on the m bit (see figure 2.). as long as the sbk bit is set, the sci send break frames to the tdo pin. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a trans- mission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set i.e. before writing the next byte in the dr. st72334j/n, st72314j/n, st72124j 89/153 serial communications interface (contd) 14.5.5.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the cr1 reg- ister. character reception during a sci reception, data shifts in least signifi- cant bit first through the rdi pin. in this mode, dr register consists in a buffer (rdr) between the in- ternal bus and the received shift register (see fig- ure 1.). procedure C select the m bit to define the word length. C select the desired baud rate using the brr and the erpr registers. C set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: C the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. C an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. C the error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the sr register 2. a read to the dr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the sci han- dles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an in- terrupt if the ilie bit is set and the i bit is cleared in the ccr register. overrun error an overrun error occurs when a character is re- ceived when rdrf has not been reset. data can not be transferred from the shift register to the tdr register as long as the rdrf bit is not cleared. when a overrun error occurs: C the or bit is set. C the rdr content will not be lost. C the shift register will be overwritten. C an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the or bit is reset by an access to the sr register followed by a dr register read operation. noise error oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. when noise is detected in a frame: C the nf is set at the rising edge of the rdrf bit. C data is transferred from the shift register to the dr register. C no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf bit is reset by a sr register read operation followed by a dr register read operation. framing error a framing error is detected when: C the stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. C a break is received. when the framing error is detected: C the fe bit is set by hardware C data is transferred from the shift register to the dr register. C no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a sr register read operation followed by a dr register read operation. st72334j/n, st72314j/n, st72124j 90/153 serial communications interface (contd) figure 50. sci baud rate and extended prescaler block diagram transmitter receiver etpr erpr extended prescaler receiver rate control extended prescaler transmitter rate control extended prescaler clock clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /2 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register st72334j/n, st72314j/n, st72124j 91/153 serial communications interface (contd) 14.5.5.4 conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp0 & scp1 bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct0, sct1 & sct2 bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr0,scr1 & scr2 bits) all this bits are in the brr register. example: if f cpu is 8 mhz (normal mode) and if pr=13 and tr=rr=1, the transmit and receive baud rates are 19200 baud. caution: the baud rate register (scibrr) must not be written to (changed or refreshed) while the transmitter or the receiver is enabled. 14.5.5.5 extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal- er, whereas the conventional baud rate genera- tor retains industry standard software compatibili- ty. the extended baud rate generator block diagram is described in the figure 3.. the output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the erpr or the etpr register. note: the extended prescaler is activated by set- ting the etpr or erpr register to a value other than zero. the baud rates are calculated as fol- lows: with: etpr = 1,..,255 (see etpr register) erpr = 1,.. 255 (see erpr register) 14.5.5.6 receiver muting and wake-up feature in multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interrupt are inhibited. a muted receiver may be awakened by one of the following two ways: C by idle line detection if the wake bit is reset, C by address mark detection if the wake bit is set. receiver wakes-up by idle line detection when the receive line has recognised an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. receiver wakes-up by address mark detection when it received a 1 as the most significant bit of a word, thus indicating that the message is an ad- dress. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. tx = (32 * pr) * tr f cpu rx = (32 * pr) * rr f cpu tx = 16 * etpr f cpu rx = 16 * erpr f cpu st72334j/n, st72314j/n, st72124j 92/153 serial communications interface (contd) 14.5.6 low power modes 14.5.7 interrupts the sci interrupt events are connected to the same interrupt vector (see interrupts chapter). these events generate an interrupt if the corre- sponding enable control bit is set and the inter- rupt mask in the cc register is reset (rim instruc- tion). mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmitting/receiving until halt mode is exited. interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission complete tc tcie yes no received data ready to be read rdrf rie yes no overrrun error detected or yes no idle line detected idle ilie yes no st72334j/n, st72314j/n, st72124j 93/153 serial communications interface (contd) 14.5.8 register description status register (sr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie =1 in the cr2 register. it is cleared by a software se- quence (an access to the sr register followed by a write to the dr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note : data will not be transferred to the shift regis- ter as long as the tdre bit is not reset. bit 6 = tc transmission complete. this bit is set by hardware when transmission of a frame containing data, a preamble or a break is complete. an interrupt is generated if tcie=1 in the cr2 register. it is cleared by a software se- quence (an access to the sr register followed by a write to the dr register). 0: transmission is not complete 1: transmission is complete bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred into the dr register. an interrupt is generated if rie=1 in the cr2 register. it is cleared by a software sequence (an access to the sr register followed by a read to the dr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when a idle line is de- tected. an interrupt is generated if the ilie=1 in the cr2 register. it is cleared by a software se- quence (an access to the sr register followed by a read to the dr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line oc- curs). this bit is not set by an idle line when the re- ceiver wakes up from wake-up mode. bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf=1. an interrupt is generated if rie=1 in the cr2 reg- ister. it is cleared by a software sequence (an ac- cess to the sr register followed by a read to the dr register). 0: no overrun error 1: overrun error is detected note: when this bit is set rdr register content will not be lost but the shift register will be overwritten. bit 2 = nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by a software se- quence (an access to the sr register followed by a read to the dr register). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. it is cleared by a software sequence (an access to the sr register followed by a read to the dr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be transferred and only the or bit will be set. bit 0 = unused. 70 tdre tc rdrf idle or nf fe - st72334j/n, st72314j/n, st72124j 94/153 serial communications interface (contd) control register 1 (cr1) read/write reset value: undefined bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit- ted word when m=1. bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre=1 in the sr register. bit 6 = tcie transmission complete interrupt ena- ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the sr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the sr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the sr register. bit 3 = te transmitter enable. this bit enables the transmitter and assigns the tdo pin to the alternate function. it is set and cleared by software. 0: transmitter is disabled, the tdo pin is back to the i/o port configuration. 1: transmitter is enabled note: during transmission, a 0 pulse on the te bit (0 followed by 1) sends a preamble after the current word. bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled. 1: receiver is enabled and begins searching for a start bit. bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to 1 and then to 0, the transmitter will send a br eak word at the end of the current word. 70 r8 t8 - m wake - - - 70 tie tcie rie ilie te re rwu sbk st72334j/n, st72314j/n, st72124j 95/153 serial communications interface (contd) data register (dr) read/write reset value: undefined contains the received or transmitted data char- acter, depending on whether it is read from or writ- ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg- ister (see figure 1.). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 1.). baud rate register (brr) read/write reset value: 00xx xxxx (xxh) bit 7:6= scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bit 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention- al baud rate generator mode. note: this tr factor is used only when the etpr fine tuning factor is equal to 00h; otherwise, tr is replaced by the etpr dividing factor. bit 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. note: this rr factor is used only when the erpr fine tuning factor is equal to 00h; otherwise, rr is replaced by the erpr dividing factor. 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 100 301 410 13 1 1 tr dividing factor sct2 sct1 sct0 1000 2001 4010 8011 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 rr dividing factor scr2 scr1 scr0 1000 2001 4010 8011 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 st72334j/n, st72314j/n, st72124j 96/153 serial communications interface (contd) extended receive prescaler division register (erpr) read/write reset value: 0000 0000 (00h) allows setting of the extended prescaler rate divi- sion factor for the receive circuit. bit 7:1 = erpr[7:0] 8-bit extended receive pres- caler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 3.) is divided by the binary factor set in the erpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. extended transmit prescaler division register (etpr) read/write reset value:0000 0000 (00h) allows setting of the external prescaler rate divi- sion factor for the transmit circuit. bit 7:1 = etpr[7:0] 8-bit extended transmit pres- caler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 3.) is divided by the binary factor set in the etpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. table 18. sci register map and reset values 70 erpr 7 erpr 6 erpr 5 erpr 4 erpr 3 erpr 2 erpr 1 erpr 0 70 etpr 7 etpr 6 etpr 5 etpr 4 etpr 3 etpr 2 etpr 1 etpr 0 address (hex.) register label 76543210 0050h scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 00 0051h scidr reset value msb xxxxxxx lsb x 0052h scibrr reset value sog 00 vpol x 2fhdet x hvsel x vcordis x clpinv x blkinv x 0053h scicr1 reset value r8 x t8 x0 m x wake x000 0054h scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 0055h scipbrr reset value msb 0000000 lsb 0 0057h scipbrt reset value msb 0000000 lsb 0 st72334j/n, st72314j/n, st72124j 97/153 14.6 8-bit a/d converter (adc) 14.6.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. the result of the conversion is stored in a 8-bit data register. the a/d converter is controlled through a control/status register. 14.6.2 main features n 8-bit conversion n up to 16 channels with multiplexed input n linear successive approximation n data register (dr) which contains the results n conversion complete status flag n on/off bit (to reduce consumption) the block diagram is shown in figure 51 . 14.6.3 functional description 14.6.3.1 analog power supply v dda and v ssa are the high and low level refer- ence voltage pins. in some devices (refer to device pin out description) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. see electrical characteristics section for more de- tails. figure 51. adc block diagram ch2 ch1 ch3 coco 0 adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux r adc c adc d2 d1 d3 d7 d6 d5 d4 d0 adcdr 4 div 2 f adc f cpu hold control st72334j/n, st72314j/n, st72124j 98/153 8-bit a/d converter (adc) (contd) 14.6.3.2 digital a/d conversion result the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than or equal to v dda (high-level voltage reference) then the conversion result in the dr register is ffh (full scale) without overflow indication. if input voltage (v ain ) is lower than or equal to v ssa (low-level voltage reference) then the con- version result in the dr register is 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdr register. the accuracy of the conversion is described in the parametric section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 14.6.3.3 a/d conversion phases the a/d conversion is based on two conversion phases as shown in figure 52 : n sample capacitor loading [duration: t load ] during this phase, the v ain input voltage to be measured is loaded into the c adc sample capacitor. n a/d conversion [duration: t conv ] during this phase, the a/d conversion is computed (8 successive approximations cycles) and the c adc sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. while the adc is on, these two phases are contin- uously repeated. at the end of each conversion, the sample capaci- tor is kept loaded with the previous measurement load. the advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement. 14.6.3.4 software procedure refer to the control/status register (csr) and data register (dr) in section 14.6.6 for the bit defini- tions and to figure 52 for the timings. adc configuration the total duration of the a/d conversion is 12 adc clock periods (1/f adc =2/f cpu ). the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the csr register: C select the ch[3:0] bits to assign the analog channel to be converted. adc conversion in the csr register: C set the adon bit to enable the a/d converter and to start the first conversion. from this time on, the adc performs a continuous conver- sion of the selected channel. when a conversion is complete C the coco bit is set by hardware. C no interrupt is generated. C the result is in the dr register and remains valid until the next conversion has ended. a write to the csr register (with adon set) aborts the current conversion, resets the coco bit and starts a new conversion. figure 52. adc conversion timings 14.6.4 low power modes note : the a/d converter may be disabled by reset- ting the adon bit. this feature allows reduced power consumption when no conversion is needed and between single shot conversions. 14.6.5 interrupts none mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d con- verter requires a stabilisation time before ac- curate conversions can be performed. adccsr write adon coco bit set t load t conv operation hold control st72334j/n, st72314j/n, st72124j 99/153 8-bit a/d converter (adc) (contd) 14.6.6 register description control/status register (csr) read/write reset value: 0000 0000 (00h) bit 7 = coco conversion complete this bit is set by hardware. it is cleared by soft- ware reading the result in the dr register or writing to the csr register. 0: conversion is not complete 1: conversion can be read from the dr register bit 6 = reserved. must always be cleared. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off 1: a/d converter is switched on bit 4 = reserved. must always be cleared. bits 3:0 = ch[3:0] channel selection these bits are set and cleared by software. they select the analog input to convert. *note : the number of pins and the channel selec- tion varies according to the device. refer to the de- vice pinout. data register (dr) read only reset value: 0000 0000 (00h) bits 7:0 = d[7:0] analog converted value this register contains the converted analog value in the range 00h to ffh. note : reading this register reset the coco flag. 70 coco 0 adon 0 ch3 ch2 ch1 ch0 channel pin* ch3 ch2 ch1 ch0 ain0 0 0 0 0 ain1 0 0 0 1 ain2 0 0 1 0 ain3 0 0 1 1 ain4 0 1 0 0 ain5 0 1 0 1 ain6 0 1 1 0 ain7 0 1 1 1 ain8 1 0 0 0 ain9 1 0 0 1 ain10 1 0 1 0 ain11 1 0 1 1 ain12 1 1 0 0 ain13 1 1 0 1 ain14 1 1 1 0 ain15 1 1 1 1 70 d7 d6 d5 d4 d3 d2 d1 d0 st72334j/n, st72314j/n, st72124j 100/153 8-bit a/d converter (adc) (contd) table 19. adc register map and reset values address (hex.) register label 76543210 0070h adcdr reset value d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 0071h adccsr reset value coco 00 adon 00 ch3 0 ch2 0 ch1 0 ch0 0 st72334j/n, st72314j/n, st72124j 101/153 15 instruction set 15.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: C long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. C short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 20. st7 addressing mode overview note 1. at the time the instruction is executed, the program counter (pc) points to the instruction follow- ing jrxx. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination/ source pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc-128/pc+127 1) + 1 relative indirect jrne [$10] pc-128/pc+127 1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 st72334j/n, st72314j/n, st72124j 102/153 st7 addressing modes (contd) 15.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 15.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 15.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 15.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 15.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations st72334j/n, st72314j/n, st72124j 103/153 st7 addressing modes (contd) 15.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 21. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 15.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in memory, of which the ad- dress follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtrac- tion operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/ indirect instructions function jrxx conditional jump callr call relative st72334j/n, st72314j/n, st72124j 104/153 15.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four bytes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, di- rect bit, or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruc- tion using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf st72334j/n, st72314j/n, st72124j 105/153 instruction groups (contd) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > st72334j/n, st72314j/n, st72124j 106/153 instruction groups (contd) mnemo description function/example dst src h i n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z st72334j/n, st72314j/n, st72124j 107/153 16 electrical characteristics 16.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 16.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 s ). 16.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v dd =5v (for the 4.5v v dd 5.5v voltage range) and v dd =3.3v (for the 3v v dd 4v voltage range). they are given only as design guidelines and are not tested. 16.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 16.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 53 . figure 53. pin loading conditions 16.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 54 . figure 54. pin input voltage c l st7 pin v in st7 pin st72334j/n, st72314j/n, st72124j 108/153 16.2 absolute maximum ratings stresses above those listed as absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 16.2.1 voltage characteristics 16.2.2 current characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k w for reset , 10k w for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd while a negative injection is induced by v in st72334j/n, st72314j/n, st72124j 110/153 16.3 operating conditions 16.3.1 general operating conditions figure 55. f osc maximum operating frequency versus v dd supply voltage for rom devices 2) figure 56. f osc maximum operating frequency versus v dd supply voltage for flash devices 2) notes: 1. guaranteed by construction. a/d operation and resonator oscillator start-up are not guaranteed below 1mhz. 2. operating conditions with t a =-40 to +125c. 3. flash programming tested in production at maximum t a with two different conditions: v dd =5.5v, f cpu =6mhz and v dd =3.2v, f cpu =4mhz. symbol parameter conditions min max unit v dd supply voltage see figure 55 and figure 56 3.2 5.5 v f osc external clock frequency v dd 3 3.5v for rom devices v dd 3 4.5v for flash devices 0 1) 16 mhz v dd 3 3.2v 0 1) 8 t a ambient temperature range 1 suffix version 0 70 c 6 suffix version -40 85 7 suffix version -40 105 3 suffix version -40 125 f osc [mhz] supply voltage [v] 16 8 4 1 0 2.5 3.2 3.5 4 4.5 5 5.5 functionality functionality functionality guaranteed in this area not guaranteed in this area not guaranteed in this area with resonator 1) 3.85 not guaranteed in this area at t a > 85c functionality 12 not guaranteed in this area at t a > 85c f osc [mhz] supply voltage [v] 16 8 4 1 0 2.5 3.2 3.5 4 4.5 5 5.5 functionality functionality functionality guaranteed in this area 3) not guaranteed in this area not guaranteed in this area with resonator 1) 3.85 12 functionality st72334j/n, st72314j/n, st72124j 111/153 operating conditions (contd) 16.3.2 operating conditions with low voltage detector (lvd) subject to general operating conditions for v dd , f osc , and t a . figure 57. high lvd threshold versus v dd and f osc for flash devices 3) figure 58. medium lvd threshold versus v dd and f osc for flash devices 3) figure 59. low lvd threshold versus v dd and f osc for flash devices 2)4) notes: 1. lvd typical data are based on t a =25c. they are given only as design guidelines and are not tested. 2. data based on characterization results, not tested in production. 3. the v dd rise time rate condition is needed to insure a correct device power-on and lvd reset. not tested in production. 4.if the low lvd threshold is selected, when v dd falls below 3.2v, (v dd minimum operating voltage), the device is guar- anteed to continue functioning until it goes into reset state. the specified v dd min. value is necessary in the device power on phase, but during a power down phase or voltage drop the device will function below this min. level. symbol parameter conditions min typ 1) max unit v it+ reset release threshold (v dd rise) high threshold med. threshold low threshold 4.10 2) 3.75 2) 3.25 2) 4.30 3.90 3.35 4.50 4.05 3.55 v v it- reset generation threshold (v dd fall) high threshold med. threshold low threshold 4) 3.85 2) 3.50 2) 3.00 4.05 3.65 3.10 4.30 3.95 3.35 v hys lvd voltage threshold hysteresis v it+ -v it- 200 250 300 mv vt por v dd rise time rate 3) 0.2 50 v/ms t g(vdd) filtered glitch delay on v dd 2) not detected by the lvd 40 ns f osc [mhz] supply voltage [v] 16 8 0 2.5 3 3.5 4 4.5 5 5.5 functional area device under functionality and reset not guaranteed in this area for temperatures higher than 85c reset in this area functionality not guaranteed in this area v it- 3 3.85 12 f osc [mhz] supply voltage [v] 16 8 0 2.5 3 v it- 3 3.5v 4 4.5 5 5.5 functional area device under functionality and reset not guaranteed in this area for temperatures higher than 85c reset in this area functionality not guaranteed in this area 12 f osc [mhz] supply voltage [v] 16 8 0 2.5 v it- 3 3v 3.5 4 4.5 5 5.5 functional area device under functionality not guaranteed in this area for temperatures higher than 85c reset in this area functionality not guaranteed in this area 12 3.2 see note 4 st72334j/n, st72314j/n, st72124j 112/153 functional operating conditions (contd) figure 60. high lvd threshold versus v dd and f osc for rom devices 2) figure 61. medium lvd threshold versus v dd and f osc for rom devices 2) figure 62. low lvd threshold versus v dd and f osc for rom devices 2)3) notes: 1. lvd typical data are based on t a =25c. they are given only as design guidelines and are not tested. 2. the minimum v dd rise time rate is needed to insure a correct device power-on and lvd reset. not tested in production. 3. if the low lvd threshold is selected, when v dd falls below 3.2v, (v dd minimum operating voltage), the device is guar- anteed to continue functioning until it goes into reset state. the specified v dd min. value is necessary in the device power on phase, but during a power down phase or voltage drop the device will function below this min. level. f osc [mhz] supply voltage [v] 16 8 0 2.5 3 3.5 4 4.5 5 5.5 functional area device under reset in this area functionality not guaranteed in this area v it- 3 3.85 f osc [mhz] supply voltage [v] 16 8 0 2.5 3 v it- 3 3.5v 4 4.5 5 5.5 functional area device under reset in this area functionality not guaranteed in this area f osc [mhz] supply voltage [v] 16 8 0 2.5 v it- 3 3.00v 3.5 4 4.5 5 5.5 functional area device under reset in this area functionality not guaranteed in this area st72334j/n, st72314j/n, st72124j 113/153 16.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode for which the clock is stopped). 16.4.1 run and slow modes figure 63. typical i dd in run vs. f cpu figure 64. typical i dd in slow vs. f cpu notes: 1. typical data are based on t a =25c, v dd =5v (4.5v v dd 5.5v range) and v dd =3.4v (3.2v v dd 3.6v range). 2. data based on characterization results, tested in production at v dd max. and f cpu max. 3. cpu running with memory access, all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, css and lvd disabled. 4. slow mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, css and lvd disabled. symbol parameter conditions max unit d i dd( d ta) supply current variation vs. temperature constant v dd and f cpu 10 % symbol parameter conditions typ 1) max 2) unit i dd supply current in run mode 3) (see figure 63 ) 4.5v v dd 5.5v f osc =2mhz, f cpu =1mhz f osc =4mhz, f cpu =2mhz f osc =8mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 1.2 2.1 3.9 7.4 1.8 3.5 7.0 14.0 ma supply current in slow mode 4) (see figure 64 ) f osc =2mhz, f cpu =62.5khz f osc =4mhz, f cpu =125khz f osc =8mhz, f cpu =250khz f osc =16mhz, f cpu =500khz 0.4 0.5 0.7 1.0 0.9 1.1 1.4 2.0 supply current in run mode 3) (see figure 63 ) 3.2v v dd 3.6v f osc =2mhz, f cpu =1mhz f osc =4mhz, f cpu =2mhz f osc =8mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 0.3 0.8 1.6 3.5 1 1.5 3 7 supply current in slow mode 4) (see figure 64 ) f osc =2mhz, f cpu =62.5khz f osc =4mhz, f cpu =125khz f osc =8mhz, f cpu =250khz f osc =16mhz, f cpu =500khz 0.1 0.2 0.3 0.5 0.3 0.5 0.6 1.0 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 1 2 3 4 5 6 7 8 idd [ma] 8mhz 4mhz 2mhz 1mhz 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 0.2 0.4 0.6 0.8 1 1.2 idd [ma] 500khz 250khz 125khz 62.5khz st72334j/n, st72314j/n, st72124j 114/153 supply current characteristics (contd) 16.4.2 wait and slow wait modes figure 65. typical i dd in wait vs. f cpu figure 66. typical i dd in slow-wait vs. f cpu notes: 1. typical data are based on t a =25c, v dd =5v (4.5v v dd 5.5v range) and v dd =3.4v (3.2v v dd 3.6v range). 2. data based on characterization results, tested in production at v dd max. and f cpu max. 3. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, css and lvd disabled. 4. slow-wait mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, css and lvd disabled. symbol parameter conditions typ 1) max 2) unit i dd supply current in wait mode 3) (see figure 65 ) 4.5v v dd 5.5v f osc =2mhz, f cpu =1mhz f osc =4mhz, f cpu =2mhz f osc =8mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 0.35 0.7 1.3 2.5 0.6 1.2 2.1 4.0 ma supply current in slow wait mode 4) (see figure 66 ) f osc =2mhz, f cpu =62.5khz f osc =4mhz, f cpu =125khz f osc =8mhz, f cpu =250khz f osc =16mhz, f cpu =500khz 0.05 0.1 0.2 0.5 0.1 0.2 0.4 1.0 supply current in wait mode 3) (see figure 65 ) 3.2v v dd 3.6v f osc =2mhz, f cpu =1mhz f osc =4mhz, f cpu =2mhz f osc =8mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 45 150 300 500 100 300 600 1000 a supply current in slow wait mode 4) (see figure 66 ) f osc =2mhz, f cpu =62.5khz f osc =4mhz, f cpu =125khz f osc =8mhz, f cpu =250khz f osc =16mhz, f cpu =500khz 6 40 80 120 20 100 160 250 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 0.5 1 1.5 2 2.5 3 idd [ma] 8mhz 4mhz 2mhz 1mhz 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 idd [ma] 500khz 250khz 125khz 62.5khz st72334j/n, st72314j/n, st72124j 115/153 supply current characteristics (contd) 16.4.3 halt and active-halt modes 16.4.4 supply and clock managers the previous current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode). 16.4.5 on-chip peripherals notes: 1. typical data are based on t a =25c. 2. all i/o pins in input mode with a static value at v dd or v ss (no load), css and lvd disabled. data based on charac- terization results, tested in production at v dd max. and f cpu max. 3. data based on design simulation and/or technology characteristics, not tested in production. all i/o pins in input mode with a static value at v dd or v ss (no load); clock input (osc1) driven by external square wave, lvd disabled. 4. data based on characterization results, not tested in production. 5. data based on characterization results done with the external components specified in section 16.5.3 and section 16.5.4 , not tested in production. 6. as the oscillator is based on a current source, the consumption does not depend on the voltage. 7. data based on a differential i dd measurement between reset configuration (timer counter running at f cpu /4) and timer counter stopped (selecting external clock capability). data valid for one timer. 8. data based on a differential i dd measurement between reset configuration and a permanent spi master communica- tion (data sent equal to 55h). 9. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. symbol parameter conditions typ 1) max unit i dd supply current in halt mode 2) v dd =5.5v -40c t a +85c <2 10 m a -40c t a +125c 150 v dd =3.6v -40c t a +85c 6 -40c t a +125c 100 supply current in active-halt mode 3) 50 150 symbol parameter conditions typ 1) max 4) unit i dd(ck) supply current of internal rc oscillator 500 750 m a supply current of external rc oscillator 5) 525 750 supply current of resonator oscillator 5) & 6) lp: low power oscillator mp: medium power oscillator ms: medium speed oscillator hs: high speed oscillator 200 300 450 700 400 550 750 1000 clock security system supply current 150 350 i dd(lvd) lvd supply current halt mode 100 150 symbol parameter conditions typ unit i dd(tim) 16-bit timer supply current 7) f cpu =8mhz v dd = 3.4v 50 m a v dd = 5.0v 150 i dd(spi) spi supply current 8) f cpu =8mhz v dd = 3.4v 250 v dd = 5.0v 350 i dd(adc) adc supply current when converting 9) f adc =4mhz v dd = 3.4v 800 v dd = 5.0v 1100 st72334j/n, st72314j/n, st72124j 116/153 16.5 clock and timing characteristics subject to general operating conditions for v dd , f osc , and t a . 16.5.1 general timings 16.5.2 external clock source figure 67. typical application with an external clock source notes: 1. data based on typical application software. 2. time measured between interrupt event and interrupt vector fetch. d t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. 3. data based on design simulation and/or technology characteristics, not tested in production. symbol parameter conditions min typ 1) max unit t c(inst) instruction cycle time 2 3 12 t cpu f cpu =8mhz 250 375 1500 ns t v(it) interrupt reaction time 2) t v(it) = d t c(inst) + 10 10 22 t cpu f cpu =8mhz 1.25 2.75 m s symbol parameter conditions min typ max unit v osc1h osc1 input pin high level voltage see figure 67 0.7xv dd v dd v v osc1l osc1 input pin low level voltage v ss 0.3xv dd t w(osc1h) t w(osc1l) osc1 high or low time 3) 15 ns t r(osc1) t f(osc1) osc1 rise or fall time 3) 15 i l oscx input leakage current v ss v in v dd 1 m a osc1 osc2 f osc external st72xxx clock source not connected internally v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) i l 90% 10% st72334j/n, st72314j/n, st72124j 117/153 clock and timing characteristics (contd) 16.5.3 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. all the information given in this paragraph are based on characterization results with specified typical external components. in the application, the reso- nator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabiliza- tion time. refer to the crystal/ceramic resonator manufacturer for more details (frequency, pack- age, accuracy...). 16.5.3.1 typical crystal resonators figure 68. application with a crystal resonator notes: 1. resonator characteristics given by the crystal manufacturer. 2. t su(osc) is the typical oscillator start-up time measured between v dd =2.8v and the fetch of the first instruction (with a quick v dd ramp-up from 0 to 5v (<50 m s). 3. the oscillator selection can be optimized in terms of supply current using an high quality resonator with small r s value. refer to crystal manufacturer for more details. symbol parameter conditions min max unit f osc oscillator frequency 3) lp: low power oscillator mp: medium power oscillator ms: medium speed oscillator hs: high speed oscillator 1 >2 >4 >8 2 4 8 16 mhz r f feedback resistor 20 40 k w c l1 c l2 recommended load capacitance ver- sus equivalent serial resistance of the crystal or ceramic resonator (r s ) r s =200 w lp oscillator r s =200 w mp oscillator r s =200 w ms oscillator r s =100 w hs oscillator 38 32 18 15 56 46 26 21 pf i 2 osc2 driving current v dd =5v lp oscillator v in =v ss mp oscillator ms oscillator hs oscillator 40 110 180 400 100 190 360 700 m a option byte config. reference freq. characteristic 1) c l1 [pf] c l2 [pf] t su(osc) [ms] 2) lp jauch s-200-30-30/50 2mhz d f osc =[30ppm 25c ,30ppm d ta ] , typ. r s =200 w 33 34 10~15 mp ss3-400-30-30/30 4mhz d f osc =[30ppm 25c ,30ppm d ta ] , typ. r s =60 w 33 34 7~10 ms ss3-800-30-30/30 8mhz d f osc =[30ppm 25c ,30ppm d ta ] , typ. r s =25 w 33 34 2.5~3 hs ss3-1600-30-30/30 16mhz d f osc =[30ppm 25c ,30ppm d ta ] , typ. r s =15 w 33 34 1~1.5 osc2 osc1 f osc c l1 c l2 i 2 r f st72xxx resonator st72334j/n, st72314j/n, st72124j 118/153 clock and timing characteristics (contd) 16.5.3.2 typical ceramic resonators note: t su(osc) is the typical oscillator start-up time measured between v dd =2.8v and the fetch of the first instruction (with a quick v dd ramp-up from 0 to 5v (<50 m s). figure 69. application with ceramic resonator notes: 1. resonator characteristics given by the ceramic resonator manufacturer. 2. t su(osc) is the typical oscillator start-up time measured between v dd =2.8v and the fetch of the first instruction (with a quick v dd ramp-up from 0 to 5v (<50 m s). 3. the oscillator selection can be optimized in terms of supply current using an high quality resonator with small r s value. refer to table 22 and table 23 and to the ceramic resonator manufacturers documentation for more details. symbol parameter conditions typ unit t su(osc) ceramic resonator start-up time lp 2mhz 4.2 ms mp 4mhz 2.1 ms 8mhz 1.1 hs 16mhz 0.7 osc2 osc1 f osc c l1 c l2 i 2 r f st72xxx resonator when resonator with integrated capacitors r d r f(ext) st72334j/n, st72314j/n, st72124j 119/153 clock and timing characteristics (contd) table 22. typical ceramic resonators table 23. resonator frequency correlation factor notes: 1. murata ceralock 2. v dd 4.5 to 5.5v 3. values in parentheses refer to the capacitors integrated in the resonator option byte config. f osc (mhz) resonator part number 1) c l1 [pf] 3 c l2 [pf] 3 r fext k w r d [k w ] lp 1 csb1000ja 100 100 open 3.3 csbf1000ja 2 csts0200mga06 (47) (47) 0 cstcc2.00mga0h6 mp 2 csts0200mga06 cstcc2.00mga0h6 4 csts0400mga06 cstcc4.00mga0h6 ms 4 csts0400mga06 cstcc4.00mga0h6 8 csts0800mga06 cstcc8.00mga0h6 hs 8 csts0800mga06 cstcc8.00mga0h6 10 cst10.0mtwa 30 30 cstcc10.0mga (15) (15) 12 cst12.0mtwa 30 30 cstcs12.0mta (30) (30) 16 2) csa16.00mxza040 15 15 cst16.00mxwa0c3 (15) (15) csacv16.00mxa040q 15 15 10 cstcv16.00mxa0h3q (15) (15) option byte config. resonator 1) corre- lation % refer- ence ic option byte config. resonator 1) corre- lation % refer- ence ic lp csb1000ja +0.03 4069ube ms csts0400mga06 -0.03 74hcu04 csts0200mga06 -0.20 74hcu04 cstcc4.00mga0h6 -0.05 cstcc2.00mga0h6 -0.16 csts0800mga06 +0.03 mp csts0200mga06 -0.21 cstcc4.00mga0h6 +0.02 cstcc2.00mga0h6 -0.19 hs csts0800mga06 +0.02 csts0400mga06 0.02 cstcc8.00mga0h6 +0.01 cstcc4.00mga0h6 -0.05 csts10.0mtwa +0.38 4069ube cstcc10.0mga +0.61 cst12.0mtwa +0.38 cstcs12.0mta +0.42 csa16.00mxza040 +0.10 74hcu04 csacv16.00mxa040q +0.08 st72334j/n, st72314j/n, st72124j 120/153 clock characteristics (contd) 16.5.4 rc oscillators the st7 internal clock can be supplied with an rc oscillator. this oscillator can be used with internal or external components (selectable by option byte). figure 70. typical application with rc oscillator figure 71. typical internal rc oscillator figure 72. typical external rc oscillator notes: 1. data based on characterization results. 2. guaranteed frequency range with the specified c ex and r ex ranges taking into account the device process variation. data based on design simulation. 3. data based on characterization results done with v dd nominal at 5v, not tested in production. 4. r ex must have a positive temperature coefficient (ppm/c), carbon resistors should therefore not be used. 5. important: when no external c ex is applied, the capacitance to be considered is the global parasitic capacitance which is subject to high variation (package, application...). in this case, the rc oscillator frequency tuning has to be done by trying out several resistor values. symbol parameter conditions min typ max unit f osc internal rc oscillator frequency 1) see figure 71 3.60 5.10 mhz external rc oscillator frequency 2) 114 t su(osc) internal rc oscillator start-up time 3) 2.0 ms external rc oscillator start-up time 3) r ex =47k w, c ex =0pf r ex =47k w, c ex =100pf r ex =10k w, c ex =6.8pf r ex =10k w, c ex =470pf 1.0 6.5 0.7 3.0 r ex oscillator external resistor 4) see figure 72 10 47 k w c ex oscillator external capacitor 0 5) 470 pf osc1 osc2 f osc c ex r ex external rc internal rc v ref + - v dd current copy voltage generator c ex discharge st72xxx 3.2 5.5 vdd [v] 3.8 3.9 4 4.1 4.2 4.3 fosc [mhz] -40c +25c +85c +125c 0 6.8 22 47 100 270 470 cex [pf] 0 5 10 15 20 fosc [mhz] rex=10kohm rex=15kohm rex=22kohm rex=33kohm rex=39kohm rex=47kohm st72334j/n, st72314j/n, st72124j 121/153 clock characteristics (contd) 16.5.5 clock security system (css) figure 73. typical safe oscillator frequencies note: 1. data based on characterization results, tested in production between 90khz and 600khz. 2. filtered glitch on the f osc signal. see functional description in section 9.4 on page 31 for more details. symbol parameter conditions min typ max unit f sfosc safe oscillator frequency 1) t a = 25c, v dd = 5.0v 250 340 550 khz t a = 25c, v dd = 3.4v 190 260 450 f gfosc glitch filtered frequency 2) 30 mhz 3.2 5.5 vdd [v] 200 250 300 350 400 fosc [khz] -40c +25c +85c +125c st72334j/n, st72314j/n, st72124j 122/153 16.6 memory characteristics 16.6.1 ram and hardware registers 16.6.2 eeprom data memory 16.6.3 flash program memory notes: 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware reg- isters (only in halt mode). guaranteed by construction, not tested in production. 2. data based on characterization results, tested in production at t a =25c. 3. up to 16 bytes can be programmed at a time for a 4kbytes flash block (then up to 32 bytes at a time for an 8k device) 4. the data retention time increases when the t a decreases. 5. data based on reliability test results and monitored in production. symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 1.6 v symbol parameter conditions min typ max unit t prog programming time for 1~16 bytes 3) -40c t a +85c 20 ms -40c t a +125c 25 t ret data retention 5) t a = +55c 4) 20 years n rw write erase cycles 5) t a = +25c 300 000 cycles symbol parameter conditions min typ max unit t a(prog) programming temperature range 2) 02570 c t prog programming time for 1~16 bytes 3) t a = +25c 8 25 ms programming time for 4 or 8kbytes t a = +25c 2.1 6.4 sec t ret data retention 5) t a =+55c 4) 20 years n rw write erase cycles 5) t a = +25c 100 cycles st72334j/n, st72314j/n, st72124j 123/153 16.7 emc characteristics susceptibility tests are performed on a sample ba- sis during product characterization. 16.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). n esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. n ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. figure 74. emc recommended star network power supply connection 2) notes: 1. data based on characterization results, not tested in production. 2. the suggested 10 m f and 0.1 m f decoupling capacitors on the power supply lines are proposed as a good price vs. emc performance trade-off. they have to be put as close as possible to the device power supply pins. other emc recommen- dations are given in other sections (i/os, reset, oscx pin characteristics). symbol parameter conditions neg 1) pos 1) unit v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-2 -1 1 kv v fftb fast transient voltage burst limits to be ap- plied through 100pf on v dd and v dd pins to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-4 -4 4 v dd v ss 0.1 m f 10 m f v dd st72xxx v ssa v dda 0.1 m f power supply source st7 digital noise filtering external noise filtering st72334j/n, st72314j/n, st72124j 124/153 emc characteristics (contd) 16.7.2 absolute electrical sensitivity based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, re- fer to the an1181 st7 application note. 16.7.2.1 electro-static discharge (esd) electro-static discharges (3 positive then 3 nega- tive pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). two models are usually simulated: human body model and machine model. this test conforms to the jesd22-a114a/a115a standard. see figure 75 and the following test sequences. human body model test sequence C c l is loaded through s1 by the hv pulse gener- ator. C s1 switches position from generator to r. C a discharge from c l through r (body resistance) to the st7 occurs. C s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. machine model test sequence C c l is loaded through s1 by the hv pulse gener- ator. C s1 switches position from generator to st7. C a discharge from c l to the st7 occurs. C s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. C r (machine resistance), in series with s2, en- sures a slow discharge of the st7. absolute maximum ratings figure 75. typical equivalent esd circuits notes: 1. data based on characterization results, not tested in production. symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 3000 v v esd(mm) electro-static discharge voltage (machine model) t a = +25c 400 st7 s2 r=1500 w s1 high voltage c l = 100pf pulse generator st7 s2 high voltage c l = 200pf pulse generator r=10k~10m w s1 human body model machine model st72334j/n, st72314j/n, st72124j 125/153 emc characteristics (contd) 16.7.2.2 static and dynamic latch-up n lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable i/o pin) and a power supply switch sequence are performed on each sample. this test conforms to the eia/ jesd 78 ic latch-up standard. for more details, refer to the an1181 st7 application note. n dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards and is described in figure 76 . for more details, refer to the an1181 st7 application note. 16.7.2.3 designing hardened software to avoid noise problems emc characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the manage- ment of runaway conditions such as: C corrupted program counter C unexpected reset C critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the re- set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be ap- plied directly on the device, over the range of specification values. when unexpected behaviour is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note an1015). electrical sensitivities figure 76. simplified diagram of the esd generator for dlu notes: 1. class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). 2. schaffner nsg435 with a pointed test finger. symbol parameter conditions class 1) lu static latch-up class t a = +25c t a = +85c a a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25c a r ch =50m w r d =330 w c s = 150pf esd hv relay discharge tip discharge return connection generator 2) st7 v dd v ss st72334j/n, st72314j/n, st72124j 126/153 emc characteristics (contd) 16.7.3 esd pin protection strategy to protect an integrated circuit against electro- static discharge the stress must be controlled to prevent degradation or destruction of the circuit el- ements. the stress generally affects the circuit el- ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. the elements to be pro- tected must not receive excessive current, voltage or heating within their structure. an esd network combines the different input and output esd protections. this network works, by al- lowing safe discharge paths for the pins subjected to esd stress. two critical esd stress cases are presented in figure 77 and figure 78 for standard pins and in figure 79 and figure 80 for true open drain pins. standard pin protection to protect the output structure the following ele- ments are added: C a diode to v dd (3a) and a diode from v ss (3b) C a protection device between v dd and v ss (4) to protect the input structure the following ele- ments are added: C a resistor in series with the pad (1) C a diode to v dd (2a) and a diode from v ss (2b) C a protection device between v dd and v ss (4) figure 77. positive stress on a standard pad vs. v ss figure 78. negative stress on a standard pad vs. v dd in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path path to avoid in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path st72334j/n, st72314j/n, st72124j 127/153 emc characteristics (contd) true open drain pin protection the centralized protection (4) is not involved in the discharge of the esd stresses applied to true open drain pads due to the fact that a p-buffer and diode to v dd are not implemented. an additional local protection between the pad and v ss (5a & 5b) is implemented to completely absorb the posi- tive esd discharge. multisupply configuration when several types of ground (v ss , v ssa , ...) and power supply (v dd , v dda , ...) are available for any reason (better noise immunity...), the structure shown in figure 81 is implemented to protect the device against esd. figure 79. positive stress on a true open drain pad vs. v ss figure 80. negative stress on a true open drain pad vs. v dd figure 81. multisupply configuration in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path path to avoid (5a) (5b) in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path (3b) (3b) v dda v ssa v dda v dd v ss back to back diode between grounds v ssa st72334j/n, st72314j/n, st72124j 128/153 16.8 i/o port pin characteristics 16.8.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 82. two typical applications with unused i/o pin figure 83. typical i pu vs. v dd with v in =v ss notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd =5v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor (see figure 82 ). data based on design simulation and/or technology characteristics, not tested in production. 5. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics de- scribed in figure 83 ). this data is based on characterization results, tested in production at v dd max. 6. data based on characterization results, not tested in production. 7. to generate an external interrupt, a minimum pulse width has to be applied on an i/o port pin configured as an external interrupt source. symbol parameter conditions min typ 1) max unit v il input low level voltage 2) 0.3xv dd v v ih input high level voltage 2) 0.7xv dd v hys schmitt trigger voltage hysteresis 3) 400 mv i l input leakage current v ss v in v dd 1 m a i s static current consumption 4) floating input mode 200 r pu weak pull-up equivalent resistor 5) v in = v ss v dd =5v 62 120 250 k w v dd =3.3v 170 200 300 c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time 6) c l =50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time 6) 25 t w(it)in external interrupt pulse time 7) 1t cpu 10k w unused i/o port st72xxx 10k w unused i/o port st72xxx v dd 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 10 20 30 40 50 60 70 ipu [a] ta=-40c ta=25c ta=85c ta=125c st72334j/n, st72314j/n, st72124j 129/153 i/o port pin characteristics (contd) 16.8.2 output driving current subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 84. typical v ol at v dd =5v (standard) figure 85. typical v ol at v dd =5v (high-sink) figure 86. typical v oh at v dd =5v notes: 1. the i io current sunk must always respect the absolute maximum rating specified in section 16.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect the absolute maximum rating specified in section 16.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . symbol parameter conditions min max unit v ol 1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 84 and figure 87 ) v dd =5v i io =+5ma t a 85c t a 3 85c 1.3 1.5 v i io =+2ma t a 85c t a 3 85c 0.65 0.75 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 85 and figure 88 ) i io =+20ma, t a 85c t a 3 85c 1.5 1.7 i io =+8ma t a 85c t a 3 85c 0.75 0.85 v oh 2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 86 and figure 89 ) i io =-5ma, t a 85c t a 3 85c v dd -1.6 v dd -1.7 i io =-2ma t a 85c t a 3 85c v dd -0.8 v dd -1.0 0246810 iio [ma] 0 0.5 1 1.5 2 2.5 vol [v] at vdd=5v ta=-40c ta=25c ta=85c ta=125c 0 5 10 15 20 25 30 iio [ma] 0 0.5 1 1.5 2 vol [v] at vdd=5v ta=-40c ta=25c ta=85c ta=125c -8 -6 -4 -2 0 iio [ma] 1 2 3 4 5 6 voh [v] at vdd=5v ta=-40c ta=25c ta=85c ta=125c st72334j/n, st72314j/n, st72124j 130/153 i/o port pin characteristics (contd) figure 87. typical v ol vs. v dd (standard i/os) figure 88. typical v ol vs. v dd (high-sink i/os) figure 89. typical v oh vs. v dd 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.2 0.25 0.3 0.35 0.4 0.45 0.5 vol [v] at iio=2ma ta=-40c ta=25c ta=85c ta=125c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 vol [v] at iio=5ma ta=-40c ta=25c ta=85c ta=125c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 vol [v] at iio=8ma ta=-40c ta=25c ta=85c ta=125c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.5 0.7 0.9 1.1 1.3 1.5 vol [v] at iio=20ma ta=-40c ta=25c ta=85c ta=125c 3.2 3.5 4 4.5 5 5.5 vdd [v] 2 2.5 3 3.5 4 4.5 5 5.5 voh [v] at iio=-2ma ta=-40c ta=25c ta=85c ta=125c 3.5 4 4.5 5 5.5 vdd [v] 0 1 2 3 4 5 voh [v] at iio=-5ma ta=-40c ta=25c ta=85c ta=125c st72334j/n, st72314j/n, st72124j 131/153 16.9 control pin characteristics 16.9.1 asynchronous reset pin subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 90. typical application with reset pin 8) notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd =5v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. the i io current sunk must always respect the absolute maximum rating specified in section 16.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 5. the r on pull-up equivalent resistor is based on a resistive transistor (corresponding i on current characteristics de- scribed in figure 91 ). this data is based on characterization results, not tested in production. 6. to guarantee the reset of the device, a minimum pulse has to be applied to reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. 7. the reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy environments. 8. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). symbol parameter conditions min typ 1) max unit v il input low level voltage 2) 0.3xv dd v v ih input high level voltage 2) 0.7xv dd v hys schmitt trigger voltage hysteresis 3) 400 mv v ol output low level voltage 4) (see figure 92 , figure 93 ) v dd =5v i io =+5ma 0.68 0.95 v i io =+2ma 0.28 0.45 r on weak pull-up equivalent resistor 5) v in = v ss v dd =5v 20 40 60 k w v dd =3.4v 80 100 120 t w(rstl)out generated reset pulse duration external pin or internal reset sources 6 30 1/f sfosc m s t h(rstl)in external reset pulse hold time 6) 20 m s t g(rstl)in filtered glitch duration 7) 100 ns reset v dd watchdog reset st72xxx lvd reset internal r on 0.1 m f v dd 0.1 m f v dd 4.7k w external reset circuit 8) reset control option al user st72334j/n, st72314j/n, st72124j 132/153 control pin characteristics (contd) figure 91. typical i on vs. v dd with v in =v ss figure 92. typical v ol at v dd =5v (reset ) figure 93. typical v ol vs. v dd (reset ) 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 50 100 150 200 ion [a] ta=-40c ta=25c ta=85c ta=125c 012345678 iio [ma] 0 0.5 1 1.5 2 vol [v] at vdd=5v ta=-40c ta=25c ta=85c ta=125c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 vol [v] at iio=2ma ta=-40c ta=25c ta=85c ta=125c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.4 0.6 0.8 1 1.2 vol [v] at iio=5ma ta=-40c ta=25c ta=85c ta=125c st72334j/n, st72314j/n, st72124j 133/153 control pin characteristics (contd) 16.9.2 ispsel pin subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 94. two typical applications with ispsel pin 2) notes: 1. data based on design simulation and/or technology characteristics, not tested in production. 2. when the isp remote mode is not required by the application ispsel pin must be tied to v ss . symbol parameter conditions min max unit v il input low level voltage 1) v ss 0.2 v v ih input high level voltage 1) v dd -0.1 12.6 i l input leakage current v in =v ss 1 m a ispsel st72xxx 10k w programming tool ispsel st72xxx st72334j/n, st72314j/n, st72124j 134/153 16.10 timer peripheral characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output...). 16.10.1 watchdog timer 16.10.2 16-bit timer symbol parameter conditions min typ max unit t w(wdg) watchdog time-out duration 12,288 786,432 t cpu f cpu =8mhz 1.54 98.3 ms symbol parameter conditions min typ max unit t w(icap)in input capture pulse time 1 t cpu t res(pwm) pwm resolution time 2t cpu f cpu =8mhz 250 ns f ext timer external clock frequency 0 f cpu /4 mhz f pwm pwm repetition rate 0 f cpu /4 mhz res pwm pwm resolution 16 bit st72334j/n, st72314j/n, st72124j 135/153 16.11 communication interface characteristics 16.11.1 spi - serial peripheral interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). figure 95. spi slave timing diagram with cpha=0 3) notes: 1. data based on design simulation and/or characterisation results, not tested in production. 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends on the i/o port configuration. 3. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 0.0625 f cpu /4 2 mhz slave f cpu =8mhz 0 f cpu /2 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss ) ss setup time slave 120 ns t h(ss ) ss hold time slave 120 t w(sckh) t w(sckl) sck high and low time master slave 100 90 t su(mi) t su(si) data input setup time master slave 100 100 t h(mi) t h(si) data input hold time master slave 100 100 t a(so) data output access time slave 0 120 t dis(so) data output disable time slave 240 t v(so) data output valid time slave (after enable edge) 120 t h(so) data output hold time 0 t v(mo) data output valid time master (before capture edge) 0.25 t cpu t h(mo) data output hold time 0.25 ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out seenote2 cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit1 in st72334j/n, st72314j/n, st72124j 136/153 communication interface characteristics (contd) figure 96. spi slave timing diagram with cpha=1 1) figure 97. spi master timing diagram 1) notes: 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha=0 mosi input miso output cpha=0 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in ss input sck input cpha=0 mosi output miso input cpha=0 cpha=1 cpha=1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) t v(mo) t h(mo) msb in msb out bit6 in bit6 out lsb out lsb in see note 2 seenote2 cpol=0 cpol=1 cpol=0 cpol=1 t r(sck) t f(sck) st72334j/n, st72314j/n, st72124j 137/153 communications interface characteristics (contd) 16.11.2 sci - serial communications interface subject to general operating condition for v dd , f o- sc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (rdi and tdo). symbol parameter conditions standard baud rate unit f cpu accuracy vs. standard prescaler f tx f rx communication frequency 8mhz ~0.16% conventional mode tr (or rr)=64, pr=13 tr (or rr)=16, pr=13 tr (or rr)= 8, pr=13 tr (or rr)= 4, pr=13 tr (or rr)= 2, pr=13 tr (or rr)= 8, pr= 3 tr (or rr)= 1, pr=13 300 1200 2400 4800 9600 10400 19200 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 hz extended mode etpr (or erpr) = 13 38400 ~38461.54 ~0.79% extended mode etpr (or erpr) = 35 14400 ~14285.71 st72334j/n, st72314j/n, st72124j 138/153 16.12 8-bit adc characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 98. typical application with adc notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. 2. when v dda and v ssa pins are not available on the pinout, the adc refer to v dd and v ss . 3. any added external serial resistor will downgrade the adc accuracy (especially for resistance greater than 10k w ). data based on characterization results, not tested in production. 4. the stabilization time of the ad converter is masked by the first t load . the first conversion after the enable is then always valid. symbol parameter conditions min typ 1) max unit f adc adc clock frequency 4 mhz v ain conversion range voltage 2) v ssa v dda v r ain external input resistor 10 3) k w c adc internal sample and hold capacitor 6 pf t stab stabilization time after adc enable f cpu =8mhz, f adc =4mhz 0 4) m s t adc conversion time (sample+hold) 3 - sample capacitor loading time - hold conversion time 4 8 1/f adc ainx st72xxx c io ~2pf v dd i l 1 m a v t 0.6v v t 0.6v v ain r ain v dda v ssa 0.1 m f v dd adc st72334j/n, st72314j/n, st72124j 139/153 8-bit adc characteristics (contd) adc accuracy figure 99. adc accuracy characteristics notes: 1. adc accuracy vs. negative injection current: for i inj- =0.8ma, the typical leakage induced inside the die is 1.6a and the effect on the adc accuracy is a loss of 1 lsb for each 10k w increase of the external analog source impedance. this effect on the adc accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an input with analog capability, adjacent to the enabled analog input - at 5v v dd supply, and worst case temperature. 2. data based on characterization results with t a =25c. 3. data based on characterization results over the whole temperature range. symbol parameter v dd =5v, 2) f cpu =1mhz v dd =5.0v, 3) f cpu =8mhz v dd =3.3v, 3) f cpu =8mhz unit typ. max typ. max typ max |e t | total unadjusted error 1) 2.0 2.0 2.0 lsb e o offset error 1) 1.5 1.5 1.5 e g gain error 1) 1.5 1.5 1.5 |e d | differential linearity error 1) 1.5 1.5 1.5 |e l | integral linearity error 1) 1.5 1.5 1.5 e o e g 1lsb ideal 1lsb ideal v dda v ssa C 256 ---------------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 255 254 253 5 4 3 2 1 0 7 6 1234567 253 254 255 256 (1) (2) e t e d e l (3) v dda v ssa st72334j/n, st72314j/n, st72124j 140/153 17 package characteristics 17.1 package mechanical data figure 100. 64-pin thin quad flat package figure 101. 56-pin plastic dual in-line package, shrink 600-mil width dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 e 16.00 0.630 e1 14.00 0.551 e 0.80 0.031 q 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 c h l l1 e b a a1 a2 e e1 d d1 dim. mm inches min typ max min typ max a 6.35 0.250 a1 0.38 0.015 a2 3.18 4.95 0.125 0.195 b 0.41 0.016 b2 0.89 0.035 c 0.20 0.38 0.008 0.015 d 50.29 53.21 1.980 2.095 e 15.01 0.591 e1 12.32 14.73 0.485 0.580 e 1.78 0.070 ea 15.24 0.600 eb 17.78 0.700 l 2.92 5.08 0.115 0.200 number of pins n 56 e 0.015 gage plane eb eb ea e1 e c a a2 a1 e b b2 d e b st72334j/n, st72314j/n, st72124j 141/153 package mechanical data (contd) figure 102. 44-pin thin quad flat package figure 103. 42-pin plastic dual in-line package, shrink 600-mil width figure 104. thermal characteristics notes: 1. the power dissipation is obtained from the formula p d =p int +p port where p int is the chip internal power (i dd xv dd ) dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.000 0.008 d 12.00 0.472 d1 10.00 0.394 e 12.00 0.472 e1 10.00 0.394 e 0.80 0.031 q 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 44 a a2 a1 b e l1 l h c e e1 d d1 dim. mm inches min typ max min typ max a 5.08 0.200 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.38 0.46 0.56 0.015 0.018 0.022 b2 0.89 1.02 1.14 0.035 0.040 0.045 c 0.23 0.25 0.38 0.009 0.010 0.015 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.600 0.630 e1 12.70 13.72 14.48 0.500 0.540 0.570 e 1.78 0.070 ea 15.24 0.600 eb 18.54 0.730 ec 1.52 0.000 0.060 l 2.54 3.30 3.56 0.100 0.130 0.140 number of pins n 42 e e1 ea eb e 0.015 gage plane ec eb d e b b2 a2 a1 c l a st72334j/n, st72314j/n, st72124j 142/153 and p port is the port power dissipation determined by the user. 2. the average chip-junction temperature can be obtained from the formula t j = t a + p d x rthja. symbol ratings value unit r thja package thermal resistance (junction to ambient) tqfp64 sdip56 tqfp44 sdip42 60 45 52 55 c/w p d power dissipation 1) 500 mw t jmax maximum junction temperature 2) 150 c st72334j/n, st72314j/n, st72124j 143/153 17.2 soldering and glueability information recommended soldering information given only as design guidelines in figure 105 and figure 106 . recommended glue for smd plastic packages dedicated to molding compound with silicone: n heraeus: pd945, pd955 n loctite: 3615, 3298 figure 105. recommended wave soldering profile (with 37% sn and 63% pb) figure 106. recommended reflow soldering oven profile (mid jedec) 250 200 150 100 50 0 40 80 120 160 time [sec] temp. [c] 20 60 100 140 5 sec cooling phase (room temperature) preheating 80c phase soldering phase 250 200 150 100 50 0 100 200 300 400 time [sec] temp. [c] ramp up 2c/sec for 50sec 90 sec at 125c 150 sec above 183c ramp down natural 2c/sec max tmax=220+/-5c for 25 sec st72334j/n, st72314j/n, st72124j 144/153 18 device configuration and ordering information each device is available for production in user pro- grammable versions (flash) as well as in factory coded versions (rom). e 2 prom data memory and flash devices are shipped to customers with a default content (ffh), while rom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be con- figured by the customer using the option bytes while the rom devices are factory-configured. 18.1 option bytes the two option bytes allow the hardware configu- ration of the microcontroller to be selected. the option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard st7 program- ming tool). the default content of the flash is fixed to ffh. in masked rom devices, the option bytes are fixed in hardware by the rom code (see option list). user option byte 0 bit 7:2 = reserved , must always be 1. bit 1 = 56/42 package configuration . this option bit allows to configured the device ac- cording to the package. 0: 42 or 44 pin packages 1: 56 or 64 pin packages bit 0 = fmp full memory protection. this option bit enables or disables external access to the internal program memory (read-out protec- tion). clearing this bit causes the erasing (by over- writing with the currently latched values) of the whole memory (not including the option bytes). 0: program memory not read-out protected 1: program memory read-out protected note: the data e2prom is not protected by this bit in flash devices. in rom devices, a protection can be selected in the option list (see page 146 ). user option byte 1 bit 7 = css clock security system disable this option bit enables or disables the css fea- tures. 0: css enabled 1: css disabled bit 6:4 = osc[2:0] oscillator selection these three option bits can be used to select the main oscillator as shown in table 24 . bit 3:2 = lvd[1:0] low voltage detection selection these option bits enable the lvd block with a se- lected threshold as shown in table 25 . bit 1 = wdg halt watchdog reset on haltt mode this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode bit 0 = wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) table 24. main oscillator configuration table 25. lvd threshold configuration selected oscillator osc2 osc1 osc0 external clock (stand-by) 111 ~4 mhz internal rc 110 1~14 mhz external rc 10x low power resonator (lp) 011 medium power resonator (mp) 010 medium speed resonator (ms) 001 high speed resonator (hs) 000 configuration lvd1 lvd0 lvd off 11 highest voltage threshold ( ~ 4.50v) 10 medium voltage threshold ( ~ 4.05v) 01 lowest voltage threshold ( ~ 3.45v) 00 user option byte 0 70 user option byte 1 70 reserved 56/42 fmp css osc 2 osc 1 osc 0 lvd1 lvd0 wdg halt wdg sw default value 111111x011101111 st72334j/n, st72314j/n, st72124j 145/153 device configuration and ordering information (contd) 18.2 transfer of customer code customer code is made up of the rom contents and the list of the selected options (if any). the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .s19 format generated by the development tool. all un- used bytes must be set to ffh. the selected options are communicated to stmi- croelectronics using the correctly completed op- tion list appended. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. figure 107. rom factory coded device types figure 108. flash user programmable device types device package temp. range xxx / code name (defined by stmicroelectronics) 1 = standard 0 to +70 c 6 = industrial -40 to +85 c 7 = automotive -40 to +105 c 3 = automotive -40 to +125 c b = plastic dip t = plastic tqfp st72334j2, st72334j4, st72334n2, st72334n4, st72314j2, st72314j4, st72314n2, st72314n4, st72124j2 device package temp. range code name (defined by stmicroelectronics) 1 = standard 0 to +70 c 6 = industrial -40 to +85 c 7 = automotive -40 to +105 c 3 = automotive -40 to +125 c b = plastic dip t = plastic tqfp st72c334j2, st72c334j4, st72c334n2, st72c334n4, st72c314j2, st72c314j4, st72c314n2, st72c314n4, st72c124j2 xxx st72334j/n, st72314j/n, st72124j 146/153 microcontroller option list customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom code*:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . *the rom or fastrom code name is assigned by stmicroelectronics. rom or fastrom code must be sent in .s19 format. .hex extension cannot be processed. stmicroelectronics references rom type/memory size/package (check only 1 option): ------------------------------------------------------------------------------------------- rom device: | 8k | 16k | ------------------------------------------------------------------------------------------- sdip42: | [ ] st72124j2b | | | [ ] st72314j2b | [ ] st72314j4b | | [ ] st72334j2b | [ ] st72334j4b | tqfp44: | [ ] st72124j2t | | | [ ] st72314j2t | [ ] st72314j4t | | [ ] st72334j2t | [ ] st72334j4t | sdip56: | [ ] st72314n2b | [ ] st72314n4b | | [ ] st72334n2b | [ ] st72334n4b | tqfp64: | [ ] st72314n2t | [ ] st72314n4t | | [ ] st72334n2t | [ ] st72334n4t | ------------------------------------------------------------------------------------------- fastrom device:| 8k | 16k | ------------------------------------------------------------------------------------------- sdip42: | [ ] st72p124j2b | | | [ ] st72p314j2b | [ ] st72p314j4b | | [ ] st72p334j2b | [ ] st72p334j4b | tqfp44: | [ ] st72p124j2t | | | [ ] st72p314j2t | [ ] st72p314j4t | | [ ] st72p334j2t | [ ] st72p334j4t | sdip56: | [ ] st72p314n2b | [ ] st72p314n4b | | [ ] st72p334n2b | [ ] st72p334n4b | tqfp64: | [ ] st72p314n2t | [ ] st72p314n4t | | [ ] st72p334n2t | [ ] st72p334n4t | conditioning (specify for tqfp only): [ ] tape & reel [ ] tray marking: [ ] standard marking [ ] special marking (rom only): tqfp (10 char. max) : _ _ _ _ _ _ _ _ _ _ sdip (16 char. max) : _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ authorized characters are letters, digits, '.', '-', '/' and spaces only. please consult your local stmicroelectronics sales office for other marking details if required. temperature range: [ ] 0c to +70c [ ] -40c to +85c [ ] -40c to +105c [ ] -40c to +125c clock source selection: resonator: [ ] lp: low power resonator (1 to 2 mhz) [ ] mp: medium power resonator (2 to 4 mhz) [ ] ms: medium speed resonator (4 to 8 mhz) [ ] hs: high speed resonator (8 to 16 mhz) rc network: [ ] internal [ ] external external clock: [ ] clock security system: [ ] disabled [ ] enabled lvd reset: [ ] disabled [ ] enabled: [ ] highest threshold [ ] medium threshold [ ] lowest threshold watchdog selection: [ ] software activation [ ] hardware activation watchdog reset on halt: [ ] reset [ ] no reset program readout protection: [ ] disabled [ ] enabled data e2prom readout protection*: [ ] disabled [ ] enabled *available on st72334 only comments: supply operating range in the application: notes: date: signature: st72334j/n, st72314j/n, st72124j 147/153 18.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 micro- controller family. full details of tools available for the st7 from third party manufacturers can be ob- tain from the stmicroelectronics internet site: ? http//mcu.st.com. tools from these manufacturers include c compli- ers, emulators and gang programmers. stmicroelectronics tools three types of development tool are offered by st, all of them connect to a pc via a parallel (lpt) port: see table 26 and table 27 for more details. table 26. stmicroelectronics tool features table 27. dedicated stmicroelectronics development tools note : 1. in-situ programming (isp) interface for flash devices. in-circuit emulation programming capability 1) software included st7 development kit yes. (same features as hds2 emulator but without logic analyzer) yes (dip packages only) st7 cd rom with: C st7 assembly toolchain C stvd7 and wgdb7 powerful source level debugger for win 3.1, win 95 and nt C c compiler demo versions C st realizer for win 3.1 and win 95. C windows programming tools for win 3.1, win 95 and nt st7 hds2 emulator yes, powerful emulation features including trace/ logic analyzer no st7 programming board no yes (all packages) supported products st7 development kit st7 hds2 emulator st7 programming board st72(c)334j2, st72(c)334j4, st72(c)334n2, st72(c)334n4, st72(c)314j2, st72(c)314j4, st72(c)314n2, st72(c)314n4, st72(c)124j2 st7mdt2-dvp2 st7mdt2-emu2b st7mdt2-epb2/eu st7mdt2-epb2/us st7mdt2-epb2/uk st72334j/n, st72314j/n, st72124j 148/153 development tools (contd) 18.3.1 suggested list of socket types table 28. suggested list of tqfp64 socket types suggested list of tqfp44 socket types package / probe adaptor / socket reference socket type tqfp64 enplas otq-64-0.8-02 open top yamaichi ic51-0644-1240.ks-14584 clamshell emu probe yamaichi ic149-064-008-s5 smc package / probe adaptor / socket reference socket type tqfp44 enplas otq-44-0.8-04 open top yamaichi ic51-0444-467-ks-11787 clamshell tqfp44 emu probe yamaichi ic149-044-*52-s5 smc st72334j/n, st72314j/n, st72124j 149/153 18.4 st7 application notes identification description example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i2c communicating between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinusoid) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripheral registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 permanent magnet dc motor drive. an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 using the st7 spi to emulate a 16-bit slave an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer product evaluation an 910 performance benchmarking an 990 st7 benefits versus industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 application to st72f264 product optimization st72334j/n, st72314j/n, st72124j 150/153 an 982 using st7 with ceramic resonator an1014 how to minimize the st7 power consumption an1015 software techniques for improving microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1477 emulated data eeprom with xflash memory an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscil- lator programming and tools an 978 key features of the stvd7 st7 visual debug package an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an 989 getting started with the st7 hiware c toolchain an1039 st7 math utility routines an1064 writing optimized hiware c language for st7 an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ pro- gramming) an1446 using the st72521 emulator to debug a st72324 target application an1478 porting an st7 panta project to codewarrior ide an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus identification description st72334j/n, st72314j/n, st72124j 151/153 19 important notes 19.1 sci baud rate registers caution: the sci baud rate register (scibrr) must not be written to (changed or refreshed) while the transmitter or the receiver is enabled. st72334j/n, st72314j/n, st72124j 152/153 20 summary of changes description of the changes between the current release of the specification and the previous one. revision main changes date 2.5 replaced note by caution in conventional baud rate generation on page 91 changed watchdog and halt mode option to read watchdog reset on halt in section 18 please read carefully the section important notes on page 151 april-03 st72334j/n, st72314j/n, st72124j 153/153 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com |
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